SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME

• US 20160078943A1
• Filed: 07/27/2015
• Published: 03/17/2016
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamada, Kunihiro
• Granted Patent: US 9,412,454 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to one embodiment, a semiconductor memory device includes: semiconductor member; electrode member; charge accumulation member; a memory unit; and a control unit. Memory cell is formed at each crossing portion of the semiconductor member and the electrode member. The memory unit retains information indicating that the memory cell belongs to first group or second group. The control unit performs first step and second step, when reducing the charge accumulated in the charge accumulation member. In the first step, first voltage is applied both between the semiconductor member and the electrode member of the first group and between the semiconductor member and the electrode member of the second group. In the second step, second voltage is applied between the semiconductor member and the electrode member constituting the memory cell belonging to the second group.

Claims

1. A semiconductor memory device comprising:

a plurality of semiconductor members arranged along a first direction and a second direction, the second direction crossing the first direction, and the plurality of semiconductor members extending in a third direction crossing a plane including the first direction and the second direction;

a plurality of electrode members extending in a direction crossing the third direction;

a charge accumulation member provided between the semiconductor member and the electrode member, and the charge accumulation member being capable of accumulating charge;

a memory unit configured to retain information, the information indicating a memory cell belongs to a first group or a second group, the memory cell being formed at each crossing portion of the semiconductor member and the electrode member via the charge accumulation member; and

a control unit configured to perform a first step and a second step when reducing the charge accumulated in the charge accumulation member,

the first step, a first voltage being applied both between the semiconductor member and the electrode member constituting the memory cell belonging to the first group and between the semiconductor member and the electrode member constituting the memory cell belonging to the second group, the first voltage being such that potential of the electrode member is lower than potential of the semiconductor member, and

in the second step, a second voltage being applied between the semiconductor member and the electrode member constituting the memory cell belonging to the second group, the second voltage being such that potential of the electrode member is lower than potential of the semiconductor member.

2. The device according to claim 1, wherein the control unit performs the second step after the first step.

3. The device according to claim 1, wherein the control unit performs the first step after the second step.

4. The device according to claim 1, wherein the charge accumulated in the charge accumulation member is reduced less easily in the memory cell belonging to the second group than in the memory cell belonging to the first group.

5. The device according to claim 1, wherein the control unit sets the electrode member constituting the memory cell belonging to the first group to a floating state in the second step.

6. The device according to claim 1, further comprising:

a substrate,

wherein

an upper surface of the substrate is parallel to the first direction and the second direction, and

the semiconductor member, the electrode member, and the charge accumulation member are provided on the substrate.

7. The device according to claim 1, further comprising:

a substrate,

wherein

an upper surface of the substrate is parallel to the first direction and the third direction, and

the semiconductor member, the electrode member, and the charge accumulation member are provided on the substrate.

8. A semiconductor memory device comprising:

a plurality of semiconductor members arranged along a first direction and a second direction, the second direction crossing the first direction, and the plurality of semiconductor members extending in a third direction crossing a plane including the first direction and the second direction;

a plurality of electrode members extending in a direction crossing the third direction; and

a charge accumulation member provided between the semiconductor member and the electrode member, and the charge accumulation member being capable of accumulating charge,

a memory cell formed at each crossing portion of the semiconductor member and the electrode member via the charge accumulation member belonging to one of a first group and a second group, and

the semiconductor memory device being configured to perform a first step and a second step when reducing the charge accumulated in the charge accumulation member,

in the first step, a first voltage being applied both between the semiconductor member and the electrode member constituting the memory cell belonging to the first group and between the semiconductor member and the electrode member constituting the memory cell belonging to the second group, the first voltage being such that potential of the electrode member is lower than potential of the semiconductor member, and

in the second step, a second voltage being applied between the semiconductor member and the electrode member constituting the memory cell belonging to the second group, the second voltage being such that potential of the electrode member is lower than potential of the semiconductor member.

9. The device according to claim 8, wherein the charge accumulated in the charge accumulation member is reduced less easily in the memory cell belonging to the second group than in the memory cell belonging to the first group.

10. A method for driving a semiconductor memory device, the semiconductor memory device including a plurality of semiconductor members arranged along a first direction and a second direction crossing the first direction and extending in a third direction crossing a plane including the first direction and the second direction, a plurality of electrode members extending in a direction crossing the third direction, and a charge accumulation member provided between the semiconductor member and the electrode member and being capable of accumulating charge, a memory cell being formed at each crossing portion of the semiconductor member and the electrode member via the charge accumulation member, the method comprising:

reducing the charge accumulated in the charge accumulation member, including;

a first step configured to apply a first voltage both between the semiconductor member and the electrode member constituting the memory cell belonging to the first group and between the semiconductor member and the electrode member constituting the memory cell belonging to the second group, the first voltage being such that potential of the electrode member is lower than potential of the semiconductor member; and

a second step configured to apply a second voltage between the semiconductor member and the electrode member constituting the memory cell belonging to the second group, the second voltage being such that potential of the electrode member is lower than potential of the semiconductor member.

11. The method according to claim 10, wherein the second step is performed after the first step.

12. The method according to claim 10, wherein the first step is performed after the second step.

13. The method according to claim 10, wherein the charge accumulated in the charge accumulation member is reduced less easily in the memory cell belonging to the second group than in the memory cell belonging to the first group.

14. The method according to claim 10, wherein the electrode member constituting the memory cell belonging to the first group is set to a floating state in the second step.