SEMICONDUCTOR DEVICE ARRANGEMENT AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE ARRANGEMENT

• US 20160079183A1
• Filed: 09/12/2014
• Published: 03/17/2016
• Est. Priority Date: 09/12/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Santos Rodriguez, Francisco Javier
• Granted Patent: US 9,793,182 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 29/34 the imperfections being on the surface
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back side. The semiconductor substrate includes at least one electrical element formed at the semiconductor substrate front side. The semiconductor device arrangement further includes at least one porous semiconductor region formed at the semiconductor substrate back side.

Claims

1. A semiconductor device arrangement comprising:

a semiconductor substrate comprising a semiconductor substrate front side and a semiconductor substrate back side, wherein the semiconductor substrate comprises at least one electrical element formed at the semiconductor substrate front side; and

a plurality of porous semiconductor regions formed at the semiconductor substrate back side.

2. The semiconductor device arrangement according to claim 1, wherein at least part of the semiconductor substrate has a thickness which lies between 10 μ

m and 220 μ

m.

3. The semiconductor device arrangement according to claim 1, wherein the plurality of porous semiconductor regions have a porosity which lies between 5% and 95%.

4. The semiconductor device arrangement according to claim 1, wherein the semiconductor substrate comprises a plurality of chips, each chip comprising at least one electrical element at the semiconductor substrate front side, and wherein the plurality of porous semiconductor regions are formed in kerf regions between the plurality of chips.

5. The semiconductor device arrangement according to claim 1, wherein the semiconductor substrate comprises at least one chip comprising the at least one electrical element formed at a chip front side and at least one porous semiconductor region of the plurality of porous semiconductor regions formed at a chip back side.

6. The semiconductor device arrangement according to claim 1, further comprising a back side metallization layer formed over the semiconductor substrate back side, wherein the back side metallization layer at least partially covers the plurality of porous semiconductor regions.

7. The semiconductor device arrangement according to claim 1, wherein a lateral dimension of the plurality of porous semiconductor regions lies between 1 nm and 100 μ

m.

8. The semiconductor device arrangement according to claim 1, further comprising a dopant region extending to a varying depth from the semiconductor substrate back side, wherein the dopant region reaches deeper into the semiconductor substrate at a part of the semiconductor substrate comprising the plurality of porous semiconductor regions than at a part of the semiconductor substrate without the plurality of porous semiconductor regions.

21. The semiconductor device arrangement according to claim 1, wherein a vertical dimension of the plurality of porous semiconductor regions lies below 50% of a thickness of the semiconductor substrate.

22. The semiconductor device arrangement according to claim 1, wherein the at least one electrical element comprises a transistor or a diode.

9. A method for forming a semiconductor device arrangement, the method comprising:

thinning at least a portion of the semiconductor wafer to form a thinned wafer portion; and

forming a plurality of porous semiconductor regions in the semiconductor wafer, wherein the semiconductor wafer comprises a support structure laterally surrounding the thinned wafer portion of the semiconductor wafer.

10. The method according to claim 9, wherein the thinned wafer portion has a thickness which lies between 10 μ

m and 220 μ

m after thinning.

11. The method according to claim 9, wherein the portion of the semiconductor wafer is thinned so that the thinned wafer portion has a smaller thickness than the support structure, wherein the support structure comprises at least part of a remaining portion of the semiconductor wafer outside the thinned wafer portion.

12. The method according to claim 9, wherein the support structure comprises a polymer, glass or silicon arranged at an edge region of the semiconductor wafer.

13. The method according to claim 9, comprising forming the plurality of porous semiconductor regions by anodic etching at least part of the thinned portion of the semiconductor substrate.

14. The method according to claim 9, comprising forming the plurality of porous semiconductor regions at a same side of the semiconductor wafer as the support structure.

15. The method according to claim 9, wherein the plurality of porous semiconductor regions are formed in kerf regions between chip regions of the thinned wafer portion;

wherein the method further comprises individualizing the chip regions by separating the chip regions through the plurality of porous semiconductor regions.

16. The method according to claim 9, wherein the support structure has a thickness more than two times greater than the thinned wafer portion.

17. The method according to claim 9, wherein the plurality of porous semiconductor regions are formed at a back side of the thinned wafer portion of the semiconductor wafer.

18. The method according to claim 17, further comprising

introducing a dopant into the thinned wafer portion via a back side of the thinned wafer portion to form a dopant region, wherein the plurality of porous semiconductor regions comprise a higher diffusion rate of dopants passing through the plurality of porous semiconductor regions than the surrounding semiconductor material of the thinned wafer portion while introducing the dopant.

19. The method according to claim 9, further comprising forming a back side metallization layer over the back side of the thinned wafer portion, wherein the back side metallization layer at least partially covers the plurality of porous semiconductor regions.

20. A method for reducing thickness variations in a semiconductor substrate, the method comprising:

detecting at least one thickness aberration region at a side of a semiconductor substrate;

forming at least one porous semiconductor region in the at least one thickness aberration region; and

selectively removing at least part of the at least one porous semiconductor region to at least partially remove the at least one thickness aberration region.