SEMICONDUCTOR POWER MODULES AND DEVICES

• US 20160079223A1
• Filed: 11/24/2015
• Published: 03/17/2016
• Est. Priority Date: 02/24/2012
• Status: Active Grant

• Current Assignee: Transphorm Technology, Inc. (Kohlberg Kravis Roberts & Company LP)
• Original Assignee: Transphorm, Inc (Kohlberg Kravis Roberts & Company LP)
• Inventors: Wu, Yifeng
• Granted Patent: US 9,741,702 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/12 Mountings, e.g. non-detachable insulating substrates
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/117 Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H03K 17/164 : using parallel switching arrangements
• CPC Class Codes: H03K 2217/0045 : Full bridges, determining the direction of the current through the load
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 1/0263 : High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board H05K1/0293 takes precedence
• CPC Class Codes: H05K 1/162 : incorporating printed capacitors
• CPC Class Codes: H05K 2201/10015 : Non-printed capacitor
• CPC Class Codes: H05K 2201/10166 : Transistor
• CPC Class Codes: H05K 2201/10545 : Related components mounted on both sides of the PCB

Abstract

An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Claims

1. A method of forming an electronic component, comprising:

providing a first transistor encased in a first package, the first package comprising a first conductive portion having a first area, the first transistor being mounted over the first conductive portion;

providing a second transistor encased in a second package, the second package comprising a second conductive portion having a second area, the second transistor being mounted over the second conductive portion; and

providing a substrate comprising an insulating layer between a first metal layer and a second metal layer, the first metal layer being on a first side of the substrate and the second metal layer being on a second side of the substrate; and

mounting the first package on a first side of the substrate with the first conductive portion being electrically connected to the first metal layer;

mounting the second package on a second side of the substrate with the second conductive portion being electrically connected to the second metal layer;

wherein

the first package is opposite the second package, with at least 50% of the first area of the first conductive portion being opposite the second area of the second conductive portion.

2. The method of claim 1, wherein the first and second transistors are part of a half bridge circuit.

3. The method of claim 2, wherein the substrate forms a capacitor which serves to stabilize a voltage between the first and second metal layers during operation of the half bridge circuit.

4. The method of claim 3, wherein the capacitor formed by the substrate is a first capacitor, the electronic component further comprising a second capacitor connected in parallel to the first capacitor.

5. The method of claim 4, wherein the substrate includes a via hole, and a lead of the second capacitor passes through the via hole.

6. The method of claim 1, the first package having a source lead and the second package having a drain lead, wherein the source and drain leads are electrically connected to one another.

7. The method of claim 6, wherein the substrate includes a via hole, and a connector which electrically connects the source lead of the first package to the drain lead of the second package passes through the via hole.

8. The method of claim 6, wherein the first transistor has a first electrode which is electrically connected to the first conductive portion, and the second transistor has a second electrode which is electrically connected to the second conductive portion.

9. The method of claim 8, wherein the first electrode is a drain electrode of the first transistor, and the second electrode is a source electrode of the second transistor.

10. The method of claim 1, wherein the first conductive portion is directly on and contacting the first metal layer, and the second conductive portion is directly on and contacting the second metal layer.

11. The method of claim 1, wherein the first transistor or the second transistor is a III-Nitride transistor.

12. The method of claim 1, wherein the first transistor or the second transistor is a lateral device.

13. The method of claim 1, the first package having a source lead and the second package having a drain lead, and the source lead is substantially aligned with the drain lead.

14. The method of claim 1, further comprising a third transistor encased in the first package, wherein a source of the first transistor is electrically connected to a drain of the third transistor, and a gate of the first transistor is electrically connected to a source of the second transistor.

15. The method of claim 14, wherein the first transistor is a high-voltage depletion-mode transistor, and the third transistor is a low-voltage enhancement-mode transistor.

16. A method of forming an electronic component, comprising:

providing a first transistor encased in a first package, the first package having a source lead and a first conductive portion, the first transistor being mounted over the first conductive portion;

providing a second transistor encased in a second package, the second package having a drain lead and a second conductive portion, the second transistor being mounted over the second conductive portion; and

providing a substrate comprising an insulating layer between a first metal layer and a second metal layer, the first metal layer being on a first side of the substrate and the second metal layer being on a second side of the substrate; and

mounting the first package on a first side of the substrate with the first conductive portion being electrically connected to the first metal layer;

mounting the second package on a second side of the substrate with the second conductive portion being electrically connected to the second metal layer;

wherein

the first package is at least partially opposite the second package, with the source lead of the first package being substantially aligned with the drain lead of the second package.

17. The method of claim 16, wherein the substrate is a 2-layer printed circuit board (PCB) substrate.

18. The method of claim 16, wherein a drain electrode of the first transistor is electrically connected to the first conductive portion, and a source electrode of the second transistor is electrically connected to the second conductive portion.

19. The method of claim 16, wherein the first transistor and the second transistor are III-Nitride transistors.

20. The method of claim 16, wherein the first transistor and the second transistor are lateral devices.

21. A method of forming an electronic component, comprising:

providing a capacitor comprising an insulating layer between a first electrically conductive layer and a second electrically conductive layer;

providing a first transistor encased in a first package, the first package having a first conductive portion; and

providing a second transistor encased in a second package, the second package having a second conductive portion;

wherein

the first conductive portion is mounted directly over the first electrically conductive layer, and the second conductive portion is mounted directly over the second electrically conductive layer.

22. The method of claim 21, wherein the capacitor comprises a printed circuit board (PCB) substrate.

23. The method of claim 21, the first package having a drain lead and the second package having a source lead, wherein the drain lead of the first package is electrically connected to the first conductive portion, and the source lead of the second package is electrically connected to the second conductive portion.

24. The method of claim 21, wherein the electronic component comprises a half bridge module.

25. The method of claim 24, wherein the half bridge module is configured to be connected to an electrical load.

26. The method of claim 21, wherein the first conductive portion is electrically connected to the first electrically conductive layer, and the second conductive portion is electrically connected to the second electrically conductive layer.