INTEGRATED CIRCUIT HAVING A MULTIPLYING INJECTION-LOCKED OSCILLATOR

• US 20160079993A1
• Filed: 09/18/2015
• Published: 03/17/2016
• Est. Priority Date: 05/02/2011
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Daly, Barry W., Dunwell, Dustin T., Carusone, Anthony C., Eble, III, John C.
• Granted Patent: US 9,564,911 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

Claims

1. A circuit, comprising:

a first injection-locked oscillator to generate a first set of output signals, the first injection-locked oscillator having a first set of injection points, wherein each injection point in the first set of injection points is capable of receiving a corresponding input signal in a set of input signals; and

a second injection-locked oscillator to generate a second set of output signals, the second injection-locked oscillator having a second set of injection points, wherein each injection point in the second set of injection points is capable of receiving a corresponding output signal in the first set of output signals.

2. The circuit of claim 1, wherein each input signal in the set of input signals is a delayed version of a sequence of pulses.

3. The circuit of claim 2, wherein the sequence of pulses includes return-to-null pulses.

4. The circuit of claim 2, further comprising:

a pulse generator to generate the sequence of pulses; and

a chain of delay elements to generate multiple delayed versions of the sequence of pulses.

5. The circuit of claim 4, wherein the pulse generator comprises:

a first pulse generator to generate a first sequence of pulses based on a reference signal; and

a second pulse generator to generate the sequence of pulses based on the first sequence of pulses.

6. The circuit of claim 1, further comprising an output node to output an output signal from the second set of output signals.

7. The circuit of claim 1, wherein the circuit is part of a memory controller circuit that controls the operation of a memory device.

8. A method, comprising:

receiving a set of pulse-width values corresponding to a deterministic jitter pattern in an output signal of a duty cycle corrector (DCC); and

in response to determining that the minimum value in the set of pulse-width values is not substantially equal to the second minimum value in set of pulse-width values, adjusting a control input value of the DCC.

9. The method of claim 8, further comprising, in response to determining that the minimum value in the set of pulse-width values is substantially equal to the second minimum value in the set of pulse-width values, storing the control input value of the DCC.

10. A circuit, comprising:

an injection-locked oscillator to generate an output signal having a deterministic jitter pattern, the injection-locked oscillator having a set of injection points, each injection point capable of receiving an input signal in a set of input signals; and

a duty cycle corrector (DCC) to adjust pulse widths of the output signal so that the width of the narrowest pulse in the deterministic jitter pattern is substantially equal to the width of the second narrowest pulse in the deterministic jitter pattern.

11. The circuit of claim 10, wherein each input signal in the set of input signals is a delayed version of a sequence of pulses.

12. The circuit of claim 11, wherein the sequence of pulses includes return-to-null pulses.

13. The circuit of claim 10, wherein each input signal in the set of input signals is a corresponding output signal of a second injection-locked oscillator.