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METHOD AND SYSTEM FOR CONTROLLING AN INTERLEAVER

  • US 20160080000A1
  • Filed: 11/24/2015
  • Published: 03/17/2016
  • Est. Priority Date: 04/17/1998
  • Status: Active Grant
First Claim
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1. A controller for an interleaver, comprising:

  • a processor; and

    a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising;

    receiving a first signal;

    receiving a second signal; and

    generating an interleaver control signal based on the first and second signals,wherein the first signal comprises a signal to noise ratio signal, andwherein the second signal is selected from a group consisting of a data rate signal and a bit error rate signal, andwherein the first and second signals are distinct signals.

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