RECEIVER, TRANSMITTER AND DATA TRANSMISSION SYSTEM

• US 20160080111A1
• Filed: 08/14/2015
• Published: 03/17/2016
• Est. Priority Date: 09/12/2014
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Maeda, Shigeyuki, ISHll, Takanori, Kanayama, Tomoyuki
• Application Number:
  US14/826,570
• Publication Number:
  US 20160080111A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

A receiver includes a processor. The processor is configured to receive first data blocks and a first parity block from a transmitter. The first data blocks are obtained by dividing first transmission data at a predetermined size. The first parity block is generated on basis of the first data blocks. The processor is configured to restore a first missing block on basis of first received blocks and the first parity block. The first missing block is an unsuccessfully received block of the first data blocks. The first received blocks are successfully received blocks of the first data blocks. The first parity block is successfully received.

Claims

1. A receiver, comprising:

a processor configured to

receive first data blocks and a first parity block from a transmitter, the first data blocks being obtained by dividing first transmission data at a predetermined size, the first parity block being generated on basis of the first data blocks, and

restore a first missing block on basis of first received blocks and the first parity block, the first missing block being an unsuccessfully received block of the first data blocks, the first received blocks being successfully received blocks of the first data blocks, the first parity block being successfully received.

2. The receiver according to claim 1, wherein

first information is added to each of the first data blocks and the first parity block, the first information indicating a first group corresponding to the first transmission data, and

the processor is configured to

discriminate, on basis of the first information, the first received blocks and the first parity block from second data blocks and a second parity block, the second data blocks being obtained by dividing second transmission data different from the first transmission data, the second parity block being generated on basis of the second data blocks.

3. The receiver according to claim 2, wherein

second information is added to each of the first data blocks and the first parity block, the second information indicating a number of the first data blocks,

third information is added to each of the first data blocks and the first parity block, the third information indicating a serial number assigned to each of the first data blocks and the first parity block in the first group, and

the processor is configured to

determine the first missing block on basis of the second information and the third information added to each of the first received blocks and the first parity block.

4. The receiver according to claim 2, further comprising:

a buffer memory,

wherein

second information is added to each of the first data blocks and the first parity block, the second information indicating a first value or a second value different from the first value, the second information being switched between the first value and the second value every time transmission data to be transmitted is switched, and

the processor is configured to

temporarily store the first received blocks and the first parity block in the buffer memory together with the first information and the second information, and

discriminate the first received blocks and the first parity block from the second data blocks and the second parity block on basis of the first information and the second information.

5. The receiver according to claim 2, wherein

the first transmission data is requested to be written in a first memory device, and

the first information indicates a head address of a write destination area in which the first transmission data is to be written in the first memory device.

6. The receiver according to claim 5, wherein

the receiver is a storage controller for controlling access to the first memory device, and

the first transmission data is stored in a second memory device different from the first memory device.

7. A transmitter, comprising:

a buffer memory configured to

temporarily store first transmission data to be transmitted to a receiver; and

a processor configured to

obtain first data blocks by dividing the first transmission data stored in the buffer memory at a predetermined size,

generate a first parity block on basis of the first data blocks,

add first information to each of the first data blocks and the first parity block, the first information indicating a first group corresponding to the first transmission data, and

transmit the first data blocks and the first parity block together with the first information to the receiver.

8. The transmitter according to claim 7, wherein

the processor is configured to

add second information to each of the first data blocks and the first parity block, the second information indicating a number of the first data blocks,

add third information to each of the first data blocks and the first parity block, the third information indicating a serial number assigned to each of the first data blocks and the first parity block in the first group, and

transmit the first data blocks and the first parity block together with the first information, the second information, and the third information to the receiver.

9. The transmitter according to claim 7, wherein

the processor is configured to

add second information to each of the first data blocks and the first parity block, the second information indicating a first value or a second value different from the first value, and

switch the second information between the first value and the second value every time transmission data to be transmitted is switched.

10. The transmitter according to claim 7, wherein

the first transmission data is requested to be written in a first memory device, and

the first information indicates a head address of a write destination area in which the first transmission data is to be written in the first memory device.

11. The transmitter according to claim 10, wherein

the transmitter is a storage controller for controlling access to a second memory device different from the first memory device, and

the first transmission data is stored in the second memory device.

12. A data transmission system, comprising:

a transmitter including

a first processor configured to

obtain first data blocks by dividing first transmission data at a predetermined size,

generate a first parity block on basis of the first data blocks, and

transmit the first data blocks and the first parity block; and

a receiver including

a second processor configured to

receive the first data blocks and the first parity block from the transmitter, and

restore a first missing block on basis of first received blocks and the first parity block, the first missing block being an unsuccessfully received block of the first data blocks, the first received blocks being successfully received blocks of the first data blocks, the first parity block being successfully received.

13. The data transmission system according to claim 12, wherein

the first processor is configured to

add first information to each of the first data blocks and the first parity block, the first information indicating a first group corresponding to the first transmission data, and

transmit the first data blocks and the first parity block together with the first information to the receiver, and

the second processor is configured to

discriminate the first received blocks and the first parity block from second data blocks and a second parity block on basis of the first information, the second data blocks being obtained by dividing second transmission data different from the first transmission data, the second parity block being generated on basis of the second data blocks.

14. The data transmission system according to claim 13, wherein

the first processor is configured to

add second information to each of the first data blocks and the first parity block, the second information indicating a number of the first data blocks,

add third information to each of the first data blocks and the first parity block, the third information indicating a serial number assigned to each of the first data blocks and the first parity block in the first group, and

transmit the first data blocks and the first parity block together with the first information, the second information, and the third information to the receiver, and

the second processor is configured to

determine the first missing block on basis of the second information and the third information added to each of the first received blocks and the first parity block.

15. The data transmission system according to claim 13, wherein

the first processor is configured to

add second information to each of the first data blocks and the first parity block, the second information indicating a first value or a second value different from the first value, and

switch the second information between the first value and the second value every time transmission data to be transmitted is switched,

the receiver further includes a buffer memory, and

the second processor is configured to

temporarily store the first received blocks and the first parity block in the buffer memory together with the first information and the second information, and

discriminate the first received blocks and the first parity block from the second data blocks and the second parity block on basis of the first information and the second information.

16. The data transmission system according to claim 13, wherein

the first transmission data is requested to be written in a first memory device, and

the first information indicates a head address of a write destination area in which the first transmission data is to be written in the first memory device.

17. The data transmission system according to claim 16, wherein

the transmitter is a storage controller for controlling access to a second memory device different from the first memory device,

the receiver is a storage controller for controlling access to the first memory device, and

the first transmission data is stored in the second memory device.