HIGH DENSITY SERIAL OVER LAN MANAGMENT SYSTEM

• US 20160080210A1
• Filed: 05/28/2015
• Published: 03/17/2016
• Est. Priority Date: 09/11/2014
• Status: Active Grant

• Current Assignee: Quanta Computer
• Original Assignee: Quanta Computer
• Inventors: Lai, Te-Hsien, CHOU, Kai-Pei
• Granted Patent: US 10,127,170 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/105 where the programme performs an input/output emulation function
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/382 using universal interface adapter
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247

Abstract

A baseboard management controller (BMC) of a system can receive a first serial output from a first server device and a second serial output from a second server device. The BMC can send the first serial output and the second serial output to a network interface controller (NIC) for transmission over a network to a computing device.

Claims

1. A method comprising:

receiving, at a baseboard management controller (BMC), a first serial output from a first server device;

receiving, at the BMC, a second serial output from a second server device; and

sending, by the BMC, the first serial output and the second serial output to a network interface controller (NIC) for transmission over a network to a computing device.

2. The method of claim 1, further comprising:

receiving, at the NIC, a network command over the network from the computing device;

receiving, at the BMC, the network command from the NIC;

determining, by the BMC, an intended server for the network command; and

sending, by the BMC, the network command in a serial output to the intended server.

3. The method of claim 1, wherein the BMC receives the first serial output and the second serial output, transmitted according to Universal Asynchronous Receiver/Transmitter (UART) protocol.

4. The method of claim 3, wherein the BMC comprises a first BMC UART interface for receiving the first serial output and a second BMC UART interface for receiving the second serial output.

5. The method of claim 1, further comprising:

emulating, by the BMC, a first virtual BMC and a second virtual BMC;

receiving, at the first virtual BMC, the first serial output from the first server; and

receiving, at the second virtual BMC, the second serial output from the second server.

6. The method of claim 5, further comprising:

sending, by the first virtual BMC, the first serial output to the NIC; and

sending, by the second virtual BMC, the second serial output to the NIC.

7. The method of claim 5, further comprising:

receiving, at a Universal Asynchronous Receiver/Transmitter (UART) bridge, the first serial output from the first server and the second serial output from the second server, transmitted according to UART protocol;

transforming the first serial output and the second serial output from UART protocol to a bus protocol; and

sending, by the UART bridge, the first serial output and the second serial output to the BMC, transmitted according to the bus protocol.

8. The method of claim 7, wherein the UART bridge comprises a Field Programmable Gate Array (FPGA) comprising a first bridge UART interface for receiving the first serial output and a second bridge UART interface for receiving the second serial output.

9. The method of claim 7, wherein the UART bridge sends the first serial output to the BMC through a first communication bus of the bus protocol, and sends the second serial output to the BMC through a second communication bus of the bus protocol.

10. The method of claim 7, wherein the bus protocol is Inter-Integrated Circuit (IIC) protocol.

11. The method of claim 7, wherein the bus protocol is System Management Bus (SMBus) protocol.

12. The method of claim 7, wherein the UART bridge sends the first serial output and the second serial output to the BMC through a single communication bus of the bus protocol.

13. The method of claim 12, wherein the BMC comprises a dispatcher to map the first serial output and the second serial output from the single communication bus to the first virtual BMC and the second virtual BMC, respectively.

14. The method of claim 13, wherein the dispatcher uses slave addresses to distinguish the first serial output from the second serial output.

15. A system comprising:

a first server device;

a second server device;

a network interface controller (NIC);

a baseboard management controller (BMC); and

a non-transitory computer-readable medium including one or more sequences of instructions which, when executed by the BMC, causes the BMC to;

receive a first serial output from the first server;

receive a second serial output from the second server; and

send the first serial output and the second serial output to the NIC for transmission over a network to a computing device.

16. The system of claim 15, wherein the instructions further cause the BMC to:

receive, at the BMC, a network command from the NIC sent from the computing device;

determine, by the BMC, an intended server for the network command; and

send, by the BMC, the network command in a serial output to the intended server.

17. The system of claim 15, wherein the instructions further cause the BMC to:

emulate a first virtual BMC and a second virtual BMC;

receive the first serial output at the first virtual BMC; and

receive the second serial output at the second virtual BMC.

18. The system of claim 17, further comprising a UART bridge that receives the first serial output and the second serial output, transforms the first serial output and the second serial output from UART protocol to a bus protocol, and sends the first serial output and the second serial output to the BMC.

19. The system of claim 18, wherein the UART bridge sends the first serial output to the BMC through a first communication bus of the bus protocol, and sends the second serial output to the BMC through a second communication bus of the bus protocol.

20. The system of claim 18, wherein the UART bridge sends the first serial output and the second serial output to the BMC through a single communication bus of the bus protocol.