Conditional Processor Auto Boot with No Boot Loader when Coupled with a Nonvolatile Memory

• US 20160085559A1
• Filed: 09/23/2014
• Published: 03/24/2016
• Est. Priority Date: 09/23/2014
• Status: Active Grant

• Current Assignee: Dialog Semiconductors (UK) Limited
• Original Assignee: Dialog Semiconductors (UK) Limited
• Inventors: Todd, Philip
• Granted Patent: US 9,928,079 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

The use of a sleep, or halt, instruction enables a processor to halt execution when read from a non-volatile memory. The opcode for the sleep instruction is the same value as the constant bit value of an un-programmed, nonvolatile memory. When the opcode is read by the processor, execution is halted and the processor enters a wait or sleep mode. During the sleep mode, firmware is programmed into memory with another means such as an external host processor. When a valid trigger event occurs, for instance, external or internal interrupts or reset activation, the processor then exits the sleep mode and starts instruction etching at the PC_INIT address.

Claims

1. A method for immediately enabling a processor, comprising:

a) forming a sleep instruction for a processor;

b) creating an opcode for the sleep instruction to have a same value as an un-programmed memory content of a non-volatile memory; and

c) forming an instruction set, wherein the opcode associated with the un-programmed value is the sleep instruction.

2. The method of claim 1, wherein the sleep instruction when executed stops code execution.

3. The method of claim 2, wherein the code execution halted until after an external or internal event that causes firmware execution to continue.

4. The method of claim 1, wherein the opcode for the sleep instruction has a logical value of the un-programmed memory value.

5. The method of claim 1, wherein said opcode for the sleep instruction allows said processor to be enabled immediately.

6. The method of claim 5, wherein said processor behaves in a coherent manner.

7. A computer instruction, comprising:

a) an opcode assigned a same value as said un-programmed memory;

b) said opcode when executed invokes an instruction to stop processing; and

c) processing re-started after an external or internal event that causes firmware execution to continue.

8. The computer instruction of claim 7, wherein said un-programmed memory is a non-volatile memory.

9. The computer instruction of claim 8, wherein the nonvolatile memory comprises EEPROM, FLASH, OTP or other types of non-volatile memories which have a known un-programmed or erased bit value.

10. The computer instruction of claim 7, wherein the opcode to stop processing has a logical value of the un-programmed memory value.

11. The computer instruction of claim 10, wherein the opcode to stop processing instructions is a halt execution.

12. A computer instruction processing, comprising:

a) a means for a logical value in an un-programmed non-volatile memory;

b) a means for assigning said logical value to an opcode value for a halt processor execution;

c) a means for a processor reading of said un-programmed non-volatile memory; and

d) a means for halting instruction execution of said processor.

13. The computer instruction processing of claim 12, wherein said means for a logical value in an un-programmed non-volatile memory is a result of non-volatile memories having a known un-programmed bit value.

14. The computer instruction processing of claim 13, wherein said means for assigning said logical value to an opcode value for a halt processor execution with a new processor instruction that defines a SLEEP instruction, or halt processing instruction opcode that is a same value as the un-programmed bit value.

15. The computer instruction processing of claim 12, wherein said means for a processor reading of said un-programmed non-volatile memory when the processor fetches its first instruction from a default address PC-INIT and if the memory is un-programmed, then the next instruction will be the SLEEP instruction read from the un-programmed non-volatile memory.

16. The computer instruction processing of claim 12, wherein said means for halting instruction execution by said processor is dependent on the memory to be un-programmed, having a fetched value decoded into a sleep instruction wherein the processor will not attempt to read or execute any further instructions until a valid trigger event occurs.

17. The computer instruction processing of claim 12, wherein a valid trigger event comprises internal or external interrupts, wakeup triggers, or a RESET activation, which would cause the instruction fetch to start again at the PC_INIT address.