HEALTH MANAGEMENT OF NON-VOLATILE MEMORY

• US 20160085612A1
• Filed: 04/14/2015
• Published: 03/24/2016
• Est. Priority Date: 09/24/2014
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: LIU, Yi Chun
• Granted Patent: US 9,965,345 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: H03M 7/42 using table look-up for the coding or decoding process, e.g. using read-only memory H03M7/4006 takes precedence
• CPC Class Codes: H04L 1/0016 involving special memory structures, e.g. look-up tables

Abstract

An apparatus for controlling programming of a non-volatile memory including at least one block partitioned into a plurality of physical sections, each of the physical sections comprising a plurality of memory cells, the apparatus including a controller configured to access a table including information corresponding to individual ones of the plurality of physical sections. The controller is configured to identify a first programming method for a first physical section of the plurality of physical sections and identify a second programming method for a second physical section of the plurality of physical sections according to information in the table corresponding to the first and second physical sections. The controller is also configured to program the first and second physical sections according to the first and second programming methods for the first and section physical sections, respectively.

Claims

1. An apparatus for controlling programming of a non-volatile memory including at least one block partitioned into a plurality of physical sections, each of the physical sections including a plurality of memory cells, the apparatus comprising:

a controller configured to;

access a table including information corresponding to individual ones of the plurality of physical sections;

identify a first programming method for a first physical section of the plurality of physical sections according to information in the table corresponding to the first physical section, and identify a second programming method for a second physical section of the plurality of physical sections according to information in the table corresponding to the second physical section; and

program the first and second physical sections according to the first and second programming methods for the first and second physical sections, respectively.

2. The apparatus of claim 1, wherein the first programming method corresponds to an encoding scheme for programming a first plurality of bits of data at each of the plurality of memory cells of the first physical section, and the second programming method corresponds to an encoding scheme for programming a second, lesser plurality of bits of data at each of the plurality of memory cells of the second physical section.

3. The apparatus of claim 1, wherein the table includes information indicating a number of bits per memory cell to be written to the plurality of memory cells of individual physical sections of the plurality of physical sections.

4. The apparatus of claim 1, wherein the controller is further configured to determine that a bit error rate for an individual physical section exceeds a predetermined threshold, and update the information in the table corresponding to the individual physical section to degrade a status of the corresponding physical section.

5. The apparatus of claim 4, wherein the controller is configured to determine the bit error rate for an individual physical section following programming of the individual section.

6. The apparatus of claim 5, wherein the controller is further configured to identify another one of the plurality of physical sections of the memory with a greater status based on the table when the controller determines that the bit error rate for the individual physical section exceeds the predetermined threshold, and relocate the programmed information to the identified physical section of the memory with a greater status.

7. The apparatus of claim 1, wherein, as part of the first programming method, the controller is configured to generate an error correction code word using a first error correction scheme, and as part of the second programming method the controller is configured to generate an error correction code word using a second error correction scheme different from the first error correction scheme.

8. The apparatus of claim 1, wherein each of the plurality of physical sections comprises a plurality of logical pages, and wherein the first programming method programs each of the logical pages of the physical section and the second programming method programs a fewer number of logical pages of the physical section.

9. The apparatus of claim 1, wherein the controller is configured to program one or more of the plurality of physical sections to include the table and the information.

10. A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of physical sections, each of the plurality of physical sections including a plurality of memory cells, the method comprising:

receiving a control signal for a programming operation on one or more of the physical sections;

accessing a table including information corresponding to the one or more physical sections;

identifying a first programming method for a first physical section of the one or more physical sections according to information in the table corresponding to the first physical section, and identifying a second programming method for a second physical section of the one or more physical sections according to information in the table corresponding to the second physical section; and

programming the first and second physical sections according to the first and second programming methods for the first and second physical sections, respectively.

11. The method of claim 10, wherein the first programming method corresponds to an encoding scheme for programming a first plurality of bits of data at each of the plurality of memory cells of the first physical section, and the second programming method corresponds to an encoding scheme for programming a second, lesser plurality of bits of data at each of the plurality of memory cells of the second physical section.

12. The method of claim 10, further comprising providing the table including information indicating a number of bits per memory cell to be written to the plurality of memory cells of individual physical sections of the plurality of physical sections.

13. The method of claim 10, further comprising determining that a bit error rate for an individual physical section exceeds a predetermined threshold, and updating the information in the table corresponding to the individual physical section to degrade a status of the corresponding physical section.

14. The method of claim 13, further comprising determining the bit error rate for an individual physical section following programming of the individual section.

15. The method of claim 14, further comprising identifying another one of the plurality of physical sections of the memory with a greater status based on the table when the bit error rate for the individual physical section exceeds the predetermined threshold, and relocating the programmed information to the identified physical section of the memory with a greater status.

16. The method of claim 10, further comprising, as part of the first programming method, generating an error correction code word using a first error correction scheme, and, as part of the second programming method, generating an error correction code word using a second error correction scheme different from the first error correction scheme.

17. The method of claim 10, wherein each of the plurality of physical sections comprises a plurality of logical pages, and wherein the first programming method includes programming each of the logical pages of the physical section and the second programming method includes programming a fewer number of logical pages of the physical section.

18. The method of claim 10, further comprising programming one or more of the plurality of physical sections to include the table and the information.

19. A system for controlling programming of memory, the system comprising:

a non-volatile memory device including at least one block partitioned into a plurality of physical sections, each of the physical sections including a plurality of memory cells;

a table including information corresponding to individual ones of the plurality of physical sections; and

a controller for controlling programming of the non-volatile memory device, the controller being configured to;

receive a control signal for a programming operation on one or more of the physical sections;

access the table to identify information corresponding to the one or more physical sections;

identify a first programming method for a first physical section of the one or more physical sections according to the information corresponding to the first physical section, and identify a second programming method for a second physical section of the one or more physical sections according to the information corresponding to the second physical section; and

program the first and second physical sections according to the first and second programming methods for the first and second physical sections, respectively.

20. The system of claim 19, wherein the controller is further configured to determine that a bit error rate for the first or second physical section exceeds a predetermined threshold, and update the information in the table corresponding to the respective physical section to degrade a status of that physical section.