Please download the dossier by clicking on the dossier button x
×

MEMORY NODE ERROR CORRECTION

  • US 20160085653A1
  • Filed: 04/30/2013
  • Published: 03/24/2016
  • Est. Priority Date: 04/30/2013
  • Status: Active Grant
First Claim
Patent Images

1. A memory network comprising:

  • memory nodes, wherein each memory node includes memory and memory controller logic;

    inter-node links connecting the memory nodes with each other,wherein the memory controller logic of a memory node in the memory network is to receive a memory access request from a main memory controller of a processor connected to the memory network and detect an error in data for the memory access, anda resiliency group for the memory node to provide error correction for the detected error, the resiliency group including at least one memory node in the memory network.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×