MEMORY NODE ERROR CORRECTION

• US 20160085653A1
• Filed: 04/30/2013
• Published: 03/24/2016
• Est. Priority Date: 04/30/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Li, Sheng, Jouppi, Norman Paul, Faraboschi, Paolo, Yoon, Doe Hyun, Barron, Dwight L.
• Granted Patent: US 9,823,986 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/2094 Redundant storage or storage space G06F11/2056 takes precedence
• CPC Class Codes: G06F 2201/805 Real-time
• CPC Class Codes: G06F 2201/85 Active fault masking without idle spares
• CPC Class Codes: G06F 2211/1059 Parity-single bit-RAID5, i.e. RAID 5 implementations

Abstract

According to an example, a resiliency group for a memory node in a memory network can provide error correction for a memory access in the memory node. The memory access may be received from a main memory controller of a processor connected to the memory network. The memory access may be executed by a memory controller of the memory node.

Claims

1. A memory network comprising:

memory nodes, wherein each memory node includes memory and memory controller logic;

inter-node links connecting the memory nodes with each other,

wherein the memory controller logic of a memory node in the memory network is to receive a memory access request from a main memory controller of a processor connected to the memory network and detect an error in data for the memory access, and

a resiliency group for the memory node to provide error correction for the detected error, the resiliency group including at least one memory node in the memory network.

2. The memory network of claim 1, wherein the resiliency group comprises a plurality of the memory nodes, including the memory node executing the memory access and another memory node connected to the memory node by one of the plurality of inter-node links.

3. The memory network of claim 2, wherein the plurality of memory nodes in the resiliency group are neighbors to the memory node for the memory access.

4. The memory network of claim 1, wherein an access group including a memory node for the memory access is to detect the error, and the resiliency group to correct the error includes multiple memory nodes.

5. The memory network of claim 1, wherein the memory controller logic of the memory node executing the memory access is to:

determine a source of the error;

determine whether the error can be corrected by the memory controller logic of the memory node executing the memory access; and

correct the error in response to determining the error can be corrected by the memory controller logic.

6. The memory network of claim 5, wherein the memory controller logic of the memory node executing the memory access is to:

determine whether the error can be corrected by the resiliency group in response to determining the error cannot be corrected by the memory controller logic of the memory node; and

communicate with the resiliency group to correct the error in response to determining the error can be corrected by the resiliency group.

7. The memory network of claim 1, wherein the memory network employs a tree structure and the resiliency group includes memory nodes in a parent-child relationship with the memory node receiving the memory access request.

8. The memory network of claim 1, wherein a number of memory nodes in the resiliency group is determined based on performance, resiliency, and storage overhead.

9. The memory network of claim 1, wherein the memory controller logic in the memory node decomposes the memory access request into a group of read or write commands to be executed by the resiliency group.

10. The memory network of claim 9, wherein the memory node has a redundant memory node in the network and the memory node and the redundant memory node share a state of the execution of the group of read or write commands.

11. The memory network of claim 1, wherein a memory node in the memory network is to determine whether a lane in one of the links or an entire link failed, and to utilize another lane in the link or a different link in response to detecting the failure.

13. The memory mode of claim 11, wherein the memory controller logic is to detect an error for a memory access in the stacked memory, and to correct the error using at least one of the RS symbols.

12. A memory node comprising:

a stacked memory including a plurality of memory layers;

a base logic layer including memory controller logic to perform memory accesses on the stacked memory; and

vias connected to the plurality of layers to the base logic layer, wherein

the base logic layer is to determine Reed-Solomon (RS) symbols for each memory bank or subarray in a different layer and a different vertical slice of the stacked memory, and each RS symbol provides error correction for the memory bank or subarray.

14. A method comprising:

receiving a memory access request from a main memory controller of a processor at a memory node, wherein the memory node includes memory controller logic and memory;

executing the memory access in the memory by the memory controller of the memory node;

detecting an error of the memory access by the memory controller logic; and

correcting the error by the memory controller logic or correcting the error by a resiliency group of the memory node.

15. The method of claim 14, wherein the error is corrected by the resiliency group if the error cannot be corrected by the memory controller logic without the resiliency group.