Activity-Driven Capacitance Reduction to Reduce Dynamic Power Consumption in an Integrated Circuit

• US 20160085900A1
• Filed: 09/22/2014
• Published: 03/24/2016
• Est. Priority Date: 09/22/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Chandra, Amit, Rajagopal, Karthik, Velayoudame, Muthukumaravelu, Bhutani, Praveen, Mehta, Sunil
• Granted Patent: US 9,292,648 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Claims

1. A method comprising:

simulating, on a computer, a design for an integrated circuit, wherein the simulating is performed with at least one input stimulus;

responsive to the simulating, identifying a plurality of conductors in the integrated circuit that have a highest amount of switching activity in response to the input stimulus;

providing one or more constraints for the plurality of conductors to a routing tool that generates descriptions of metal layers for the integrated circuit, wherein the metal layers implement interconnects of the integrated circuit including the plurality of conductors, wherein the routing tool is configured to route the plurality of conductors responsive to the constraints, and wherein the constraints comprise a restriction that routing the plurality of conductors is to occur in one or more of the metal layers nearest a surface of a semiconductor substrate on which the integrated circuit is formed, excluding one or more metal layers that are farthest from the surface; and

providing one or more timing-derived constraints to the routing tool, wherein the routing tool is configured to favor the one or more timing-derived constraints over the one or more constraints in routing the plurality of conductors.

2. The method as recited in claim 1 wherein the constraints comprise a wire width limit.

3. The method as recited in claim 1 wherein the constraints comprise a wire spacing specification.

5. The method as recited in claim 1 wherein the constraints comprise a reduction in input pin capacitance on one or more cells to which a given conductor of the plurality of conductors is coupled.

6. The method as recited in claim 1 wherein the constraints cause reduced capacitance on the plurality of conductors compared to unconstrained routing.

7. The method as recited in claim 1 wherein the at least one input stimulus causes high power consumption in the integrated circuit.

8. The method as recited in claim 1 wherein the providing comprises annotating an input data structure to the routing tool, wherein the input data structure includes description of the plurality of conductors, and wherein the annotating associates the constraints with the plurality of conductors.

9. The method as recited in claim 8 wherein the data structure further includes the one or more timing-derived constraints.

4. (canceled)

10. A computer accessible storage medium storing a plurality of instructions which, when executed by a computer:

invoke a simulation of an integrated circuit, wherein the simulating is performed with at least one input stimulus;

responsive to the simulation, identify a plurality of nets in the integrated circuit that have a highest amount of switching activity in response to the input stimulus; and

provide one or more constraints for the plurality of nets to a routing tool that generates descriptions of metal layers for the integrated circuit that implement the nets of the integrated circuit, wherein the nets include the plurality of nets that have the highest amount of switching activity, wherein the routing tool is configured to route the plurality of nets responsive to the constraints, wherein the constraints comprise a reduction in input pin capacitance on one or more cells to which a given net of the plurality of nets is coupled by selecting a different, but logically equivalent, cell from a cell library, wherein the different cell has a lower input pin capacitance.

11. The computer accessible storage medium as recited in claim 10 further storing the routing tool.

12. The computer accessible storage medium as recited in claim 11 further storing an input data structure to the routing tool, wherein the input data structure includes description of the plurality of nets, and wherein providing the constraints includes annotating the input data structure to the routing tool and associating the constraints with the plurality of nets.

13. The computer accessible storage medium as recited in claim 12 wherein the data structure further includes timing-derived constraints, and wherein the routing tool is configured to favor timing-derived constraints over the constraints provided for the plurality of nets.

14. The computer accessible storage medium as recited in claim 10 wherein the constraints cause reduced capacitance on the plurality of nets compared to unconstrained routing.

15. The computer accessible storage medium as recited in claim 14 wherein the constraints comprise a wire width limit.

16. The computer accessible storage medium as recited in claim 15 wherein the constraints comprise a wire spacing specification.

17. The computer accessible storage medium as recited in claim 16 wherein the constraints comprise a restriction to one or more of the metal layers nearest a surface of a semiconductor substrate on which the integrated circuit is formed.

19. The method as recited in claim 10 wherein the input stimulus causes high power consumption in the integrated circuit.

18. (canceled)

20. A method comprising:

simulating an integrated circuit on a computer responsive to a first description of the integrated circuit, wherein the simulating is performed with at least one input stimulus that causes high power consumption in the integrated circuit;

responsive to the simulating, identifying a plurality of nets interconnecting circuitry in the integrated circuit, wherein the plurality of nets that have a highest amount of switching activity of the nets in the integrated circuit in response to the input stimulus; and

annotating a second description of the integrated circuit that is input to a routing tool that generates descriptions of metal layers for the integrated circuit, wherein the metal layers of the integrated circuit implement the interconnect of the integrated circuit including the plurality of nets, wherein the routing tool is configured to route the plurality of nets responsive to the constraints, wherein the constraints comprise a reduction in input pin capacitance on one or more cells to which a given net of the plurality of nets is coupled by selecting a different, but logically equivalent, cell from a cell library, wherein the different cell has a lower input pin capacitance.