Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle
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Abstract
Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.
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Citations
41 Claims
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1-21. -21. (canceled)
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22. A semiconductor memory cell comprising:
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a floating body region; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region; wherein applying a positive voltage to said substrate region and applying a zero voltage to said first region or said second region results in at least two stable floating body charge levels. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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30. A semiconductor memory array comprising:
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a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each semiconductor memory cell comprises; a silicon controlled rectifier device having a cathode region, a floating body region, a buried layer region, and an anode region, wherein; a state of said memory cell is stored in said floating body region, said buried layer region is located below said floating body region, said anode region is located below said buried layer region, and wherein said anode region is commonly connected to at least two of said memory cells, and wherein applying a voltage to said anode region results in at least two stable floating body charge levels. - View Dependent Claims (31, 32, 33, 34, 35, 36, 40)
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37. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises; a silicon controlled rectifier device having a cathode region, a floating body region, a buried layer region, and an anode region, wherein; a state of said memory cell is stored in said floating body region, said buried layer region is located below said floating body region, said anode region is located below said buried layer region, and wherein said anode region is commonly connected to at least two of said memory cells, and when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, application of a bias via said anode region maintains said first memory cell in said first state and said second memory cell in said second state. - View Dependent Claims (38, 39, 41)
Specification