METAL-GATE WITH AN AMORPHOUS METAL LAYER

• US 20160086805A1
• Filed: 02/19/2015
• Published: 03/24/2016
• Est. Priority Date: 09/24/2014
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Xu, Jeffrey Junhao, Wang, Zhongze, Rim, Kern, Song, Stanley Seungchul, Yeap, Choh Fei
• Application Number:
  US14/626,293
• Publication Number:
  US 20160086805A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A particular semiconductor device includes a substrate, a source contact, a drain contact, and a metal-gate. The substrate includes a source region, a drain region, and a channel. The source contact is coupled to the source region. The drain contact is coupled to the drain region. The metal-gate is coupled to the channel. The metal-gate includes an amorphous metal layer.

Claims

1. A semiconductor device comprising:

a substrate including a source region, a drain region, and a channel;

a source contact coupled to the source region;

a drain contact coupled to the drain region; and

a metal-gate coupled to the channel, the metal-gate including an amorphous metal layer.

2. The semiconductor device of claim 1, wherein the source contact and the drain contact exclude a silicide material.

3. The semiconductor device of claim 1, wherein the amorphous metal layer is unannealed.

4. The semiconductor device of claim 1, wherein the source contact and the drain contact are formed by depositing titanium (Ti) on the source region and the drain region of the substrate, and wherein the Ti is deposited such that a temperature of the amorphous metal layer remains below a crystallization temperature of the amorphous metal layer.

5. The semiconductor device of claim 1, wherein the source contact includes a first titanium layer and the drain contact includes a second titanium (Ti) layer.

6. The semiconductor device of claim 5, wherein the substrate includes a silicon (Si) fin, wherein the source region includes a first silicon phosphorous (SiP) layer embedded in a first portion of the Si fin, and wherein the drain region includes a second SiP layer embedded in a second portion of the Si fin.

7. The semiconductor device of claim 6, wherein the source contact is coupled via a first titanium dioxide (TiO₂) layer to the first SiP layer and the drain contact is coupled via a second TiO₂ layer to the second SiP layer.

8. The semiconductor device of claim 1, wherein the substrate includes a silicon (Si) fin, wherein the source region includes a first silicon germanium (SiGe) layer embedded in a first portion of the Si fin, and wherein the drain region includes a second SiGe layer embedded in a second portion of the Si fin.

9. The semiconductor device of claim 1, wherein the substrate includes a silicon germanium (SiGe) fin, wherein the source region includes a first SiGe layer embedded in a first portion of the SiGe fin, and wherein the drain region includes a second SiGe layer embedded in a second portion of the SiGe fin.

10. The semiconductor device of claim 1, wherein the amorphous metal layer includes a metal, a metal alloy, or an intermetallic layer, and wherein the amorphous metal layer includes at least one of tungsten (W), tantalum (Ta), aluminum (Al), cobalt (Co), titanium (Ti), and platinum (Pt).

11. The semiconductor device of claim 10, wherein the amorphous metal layer includes at least one of silicon (Si), carbon (C), and nitrogen (N).

12. A method of fabricating a semiconductor device comprising:

forming a metal-gate on a substrate, the metal-gate including an amorphous metal layer; and

depositing a second material on a source region and a drain region of the substrate, the second material deposited such that the amorphous metal layer remains amorphous.

13. The method of claim 12, wherein forming the metal-gate includes:

removing an amorphous silicon (Si) dummy gate from the substrate,

forming a silicon dioxide (SiO₂) layer on the substrate, and

depositing a high dielectric constant (high-K) layer on the SiO₂ layer,

wherein the substrate includes an Si fin.

14. The method of claim 13, wherein forming the metal-gate includes depositing a titanium nitride (TiN) layer on the high-K layer.

15. The method of claim 14, wherein forming the metal-gate includes depositing a tantalum nitride (TaN) barrier layer on the TiN layer.

16. The method of claim 15, wherein forming the metal-gate includes depositing the amorphous metal layer on the TaN barrier layer.

17. The method of claim 16, wherein forming the metal-gate includes depositing a TiN barrier layer on the amorphous metal layer.

18. The method of claim 17, wherein forming the metal-gate includes depositing a tungsten (W) layer on the TiN barrier layer.

19. The method of claim 12, further comprising:

etching a first recess in a first inter-layer dielectric (ILD) layer,

wherein the substrate includes a silicon (Si) fin,

wherein the source region includes a first silicon phosphorous (SiP) layer embedded in a first portion of the Si fin, and

wherein the first ILD layer is on the source region; and

forming a first silicon dioxide (SiO₂) layer on the first SiP layer.

20. The method of claim 19, further comprising:

etching a second recess in a second ILD layer,

wherein the drain region includes a second SiP layer embedded in a second portion of the Si fin, and

wherein the second ILD layer is on the drain region; and

forming a second SiO₂ layer on the second SiP layer.

21. The method of claim 20, wherein the second material is deposited in the first recess and the second recess, and wherein the second material includes titanium (Ti).

22. The method of claim 12, further comprising:

etching a first recess in a first interlayer dielectric (ILD) layer,

wherein the substrate includes a silicon (Si) fin,

wherein the source region includes a first silicon germanium (SiGe) layer embedded in a first portion of the Si fin, and

wherein the first ILD layer is on the source region; and

forming a first silicon germanium dioxide (SiGeO₂) layer on the first SiGe layer.

23. The method of claim 22, further comprising:

etching a second recess in a second ILD layer,

wherein the drain region includes a second SiGe layer embedded in a second portion of the Si fin, and

wherein the second ILD layer is on the drain region; and

forming a second SiGeO₂ layer on the second SiGe layer.

24. The method of claim 23, further comprising removing the first SiGeO₂ layer and the second SiGeO₂ layer prior to depositing the second material in the first recess and the second recess, wherein the second material includes titanium (Ti).

25. The method of claim 24, wherein the second material is deposited using physical vapor deposition (PVD).

26. The method of claim 24, further comprising depositing a titanium nitride (TiN) barrier layer on the second material.

27. The method of claim 26, further comprising filling the first recess and the second recess with tungsten (W).

28. A semiconductor device fabricated by a process comprising:

forming a metal-gate on a substrate, the metal-gate including an amorphous metal layer; and

depositing a second material on a source region and a drain region of the substrate, wherein the second material is deposited such that the amorphous metal layer remains amorphous.

29. The semiconductor device of claim 28, wherein the second material is deposited using physical vapor deposition (PVD).

30. The semiconductor device of claim 28, wherein the second material includes titanium (Ti).