Electronic Component

• US 20160086881A1
• Filed: 09/18/2014
• Published: 03/24/2016
• Est. Priority Date: 09/18/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Standing, Martin
• Granted Patent: US 9,559,056 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/2413 Connecting within a semiconductor or solid-state body
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence

Abstract

In an embodiment, an electronic component includes a dielectric core layer having a first major surface, a semiconductor die embedded in the dielectric core layer, and a first conductive layer. The semiconductor die includes a first major surface and at least two conductive fingers arranged on the first major surface which are coupled to a common potential. The first conductive layer is arranged on, and electrically coupled to, the at least two conductive fingers and extends from the at least two conductive fingers over the first major surface of the dielectric core layer.

Claims

1. An electronic component, comprising:

a dielectric core layer having a first major surface,

a semiconductor die embedded in the dielectric core layer, the semiconductor die comprising a first major surface and at least two conductive fingers arranged on the first major surface which are coupled to a common potential,

a first conductive layer arranged on, and electrically coupled to, the at least two conductive fingers and extending from the at least two conductive fingers over the first major surface of the dielectric core layer.

2. The electronic component according to claim 1, wherein

the semiconductor die comprises a lateral transistor.

3. The electronic component according to claim 2, wherein the at least two conductive fingers are coupled to a source or a drain of the lateral transistor.

4. The electronic component according to claim 2, wherein

the lateral transistor is a GaN-based HEMT (High Electron Mobility Transistor).

5. The electronic component according to claim 1, further comprising at least two further conductive fingers interdigitated with the at least two conductive fingers, wherein the at least two further conductive fingers are coupled to a second common potential.

6. The electronic component according to claim 1, wherein the first conductive layer has a proximal end arranged on the at least two conductive fingers and a distal end arranged at the periphery of the dielectric core layer.

7. The electronic component according to claim 1, wherein

the at least two conductive fingers have a length and a portion of the length is uncovered by the first conductive layer.

8. The electronic component according to claim 1, further comprising a second conductive layer arranged on the at least two conductive fingers and underneath the first conductive layer.

9. The electronic component according to claim 8, wherein

the at least two conductive fingers have a length, the second conductive layer is arranged on substantially the entire length of the at least two conductive fingers and a portion of the length is uncovered by the first conductive layer.

10. The electronic component according to claim 1, further comprising a third conductive layer arranged on the first conductive layer and extending between the at least two conductive fingers over the semiconductor die.

11. The electronic component according to claim 10, wherein the third conductive layer is arranged at least 20 μ

m above the surface of the semiconductor die.

12. The electronic component according to claim 10, wherein

the third conductive layer has a proximal end arranged on the semiconductor die and a distal end arranged at the periphery of the dielectric core layer.

13. The electronic component according to claim 12, wherein

the distal end comprises an outer contact pad of the electronic component.

14. The electronic component according to claim 10, wherein the third conductive layer is arranged on, and is electrically insulated from, distal portions of at least two further conductive fingers that are interdigitated with the at least two conductive fingers, and wherein the at least two further conductive fingers are coupled to a second common potential.

15. The electronic component according to claim 14, further comprising a fourth conductive layer arranged laterally adjacent and spaced apart from the third conductive layer, the fourth conductive layer being electrically coupled to the at least two further conductive fingers and extending between the at least two conductive fingers over the semiconductor die and extending to the periphery of the dielectric core layer.

16. The electronic component according to claim 15, wherein the fourth conductive layer is arranged on, and is electrically insulated from distal portions of the at least two first conductive fingers.

17. The electronic component according to claim 15, wherein the fourth conductive layer is arranged at least 20 μ

m above the surface of the semiconductor die.

18. The electronic component according to claim 15, wherein the fourth conductive layer and the third conductive layer extend from opposing sides of the semiconductor die.

21. The electronic component according to claim 1, wherein the at least two conductive fingers are coupled to a source or a drain of a transistor included in the semiconductor, and wherein further conductive fingers interdigitated with the at least two conductive fingers are coupled to the other one of the source or the drain.

19. (canceled)

20. A method of producing an electronic component, comprising:

applying a first conductive layer to at least two conductive fingers arranged on a first surface of a semiconductor die embedded in a dielectric core layer, the at least two conductive fingers being coupled to a common potential, the first conductive layer extending from the at least two conductive fingers over the first major surface of the dielectric core layer.