THREE-DIMENSIONAL NON-VOLATILE NOR-TYPE FLASH MEMORY

• US 20160086970A1
• Filed: 09/21/2015
• Published: 03/24/2016
• Est. Priority Date: 09/23/2014
• Status: Active Grant

• Current Assignee: Haibing Peng
• Original Assignee: Haibing Peng
• Inventors: Peng, Haibing
• Granted Patent: US 10,014,317 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

The present invention provides a design of three-dimensional non-volatile NOR flash memory devices consisting of arrays of basic NOR memory group in which individual memory cells (field-effect-transistors) are stacked along a direction (or directions) either out of or parallel to the plane of the substrate and electrically connected in parallel to achieve high storage densities approaching 1 TB with lower manufacturing cost. Offering full random access to every individual memory cells and also capability of parallel programming/erasing in blocks of memory cells, such three-dimensional non-volatile NOR flash memory can be widely used for both executable-code storage and mass data storage applications.

Claims

1. A basic non-volatile memory group comprising:

(i) a plurality of individual memory cells (i.e., field effect transistors) which are stacked along any direction(s) out of the plane of a substrate and electrically connected in parallel by sharing the source and drain electrodes;

(ii) a piece of semiconductor (e.g., Si or Ge) denoted as a semiconductor “

fin”

, the sidewalls or the whole body of which provide a plurality of conduction channels (with the direction of electrical current flow approximately parallel to the substrate plane) for the corresponding field-effect-transistors within the same basic memory group;

(iii) the source and drain electrodes shared by all field effect transistors are located at two opposite sides of the conduction channel (i.e. the semiconductor fin);

(iv) one or more than one side gate for each individual memory cell; and

(v) a charge trap structure (sandwiched between a gate electrode and a conduction channel) as the storage medium for memory cells.

2. The basic memory group of claim 1, wherein a plurality of individual memory cells (i.e., field effect transistors) are stacked along a direction perpendicular to the plane of the substrate and electrically connected in parallel by sharing the source and drain electrodes.

3. The basic memory group of claim 1, wherein the semiconductor fin is replaced by a stack of alternating semiconductor/insulator layers or two pieces of separated semiconductor fin to provide parallel conduction channels for the field-effect-transistors within the same basic memory group.

4. The basic memory group of claim 1 and claim 3, wherein the charge trap structure consists of an ONO structure, including a tunneling dielectric layer such as silicon oxide (O), a charge storage layer such as silicon nitride (N), and a blocking dielectric layer such as silicon oxide (O).

5. The basic memory group of claim 1 and claim 3, wherein the charge trap structure consists of a sandwiched structure, including a tunneling dielectric layer such as Al₂O₃, H_fO₂ or silicon oxide, a charge storage layer such as silicon nitride or nanometer-sized metal or semiconductor crystals, and a blocking dielectric layer such as Al₂O₃, H_fO₂ or silicon oxide.

6. The basic memory group of claim 1 and claim 3, wherein the charge trap structure consists of a bandgap engineered ONO structure where the tunneling dielectric layer includes composite materials (e.g., ultra thin silicon oxide/silicon nitride/silicon oxide structure) to assist electron tunneling.

7. The basic memory group of claim 1 and claim 3, wherein the side-gate structure consists of one or more than one stack of alternating conductor/insulator layers.

8. The basic memory group of claim 1 and claim 3, wherein the stored information of every individual memory cell can be read out via NOR gate logic.

9. A NOR memory block comprising a plurality of rows and columns of the basic memory group of claims 1-8 to form memory group arrays, wherein the Drain (Source) electrodes of a plurality of the basic memory groups (e.g., arranged in a plurality of or part of a row/column) are electrically connected to form Local Bit (Source) Lines, while the gate electrodes of a plurality of the basic memory groups (e.g., arranged in a plurality of or part of a column/row and not electrically connected to the same Local Bit/Source Lines) are electrically connected to form Word Lines.

10. A basic non-volatile memory group comprising:

(i) a plurality of individual memory cells (i.e., field effect transistors) which are stacked along any directions parallel to (or nearly parallel to) the plane of the substrate and electrically connected in parallel by sharing the source and drain electrodes;

(ii) a piece of semiconductor (e.g., a Si or Ge fin), the sidewalls or the whole body of which provide a plurality of conduction channels (with the direction of electrical current flow approximately perpendicular to the substrate plane) for the corresponding field-effect-transistors within the same basic memory group;

(iii) the source and drain electrodes shared by all field effect transistors are located above or below the conduction channel (i.e. the semiconductor fin);

(iv) one or more than one side gate for each individual memory cell; and

(v) a charge trap structure (sandwiched between a gate electrode and a conduction channel) as the storage medium for memory cells.

11. The basic memory group of claim 10, wherein the semiconductor fin is replaced by a fin with alternating semiconductor/insulator segments (e.g., p Si/SiO₂) or alternating lightly/heavily doped semiconductor segments (e.g., p Si/p+ Si) along the longitudinal direction of the fin (i.e., parallel to the substrate plane) to provide conduction channels for the field-effect-transistors within the same basic memory group.

12. The basic memory group of claim 10 and claim 11, wherein the charge trap structure consists of an ONO structure, including a tunneling dielectric layer such as silicon oxide (O), a charge storage layer such as silicon nitride (N), and a blocking dielectric layer such as silicon oxide (O).

13. The basic memory group of claim 10 and claim 11, wherein the charge trap structure consists of a sandwiched structure, including a tunneling dielectric layer such as Al₂O₃, H_fO₂ or silicon oxide, a charge storage layer such as silicon nitride or nanometer-sized metal or semiconductor crystals, and a blocking dielectric layer such as Al₂O₃, H_fO₂ or silicon oxide.

14. The basic memory group of claim 10 and claim 11, wherein the charge trap structure consists of a bandgap engineered ONO structure where the tunneling dielectric layer includes composite materials (e.g., ultra thin silicon oxide/silicon nitride/silicon oxide structure) to assist electron tunneling.

15. The basic memory group of claim 10 and claim 11, wherein the side-gate structure consists of one or more than one series of alternating conductor/insulator segments.

16. The basic memory group of claim 10 and claim 11, wherein the stored information of every individual memory cell can be read out via NOR gate logic.

17. A NOR memory block comprising a plurality of rows, columns and vertical stacks of the basic memory group of claims 10-16 to form memory group arrays, wherein the Drain (Source) electrodes of a plurality of the basic memory groups (e.g., arranged in a plurality of or part of a row/column/stack) are electrically connected to form Local Bit (Source) Lines, while the gate electrodes of a plurality of the basic memory groups (e.g., arranged in a plurality of or part of a column/row/stack and not electrically connected to the same Local Bit/Source Lines) are electrically connected to form Word Lines.

18. A memory device comprising a plurality of the NOR memory blocks of claims 9 and 17, wherein the NOR memory blocks are connected on the chip level via additional selection transistors (e.g., by connecting the Local Bit/Source Lines of the NOR memory blocks to Global Bit/Source Lines via selection transistors) and thus can be selectively addressed for read/programming/erasing operations on any individual memory cell.