MONOLITHIC THREE-DIMENSIONAL NAND STRINGS AND METHODS OF FABRICATION THEREOF

• US 20160086972A1
• Filed: 12/03/2015
• Published: 03/24/2016
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: ZHANG, Yanli, KAI, James, MAKALA, Raghuveer S., ALSMEIER, Johann, LIU, Jin, CHOWDHURY, Murshed, HUANG, Camilla
• Granted Patent: US 9,576,975 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers.

Claims

1. A monolithic three-dimensional memory device, comprising:

a vertically repeating stack of unit layer stacks, each unit layer stack comprising a conductive material layer, a lower silicon oxide material layer overlying the conductive material layer, a dielectric fill material region overlying the lower silicon oxide material layer, and an upper silicon oxide material layer overlying the dielectric fill material region;

a semiconductor channel extending through the vertically repeating stack, at least one end portion of the semiconductor channel extending substantially perpendicular to a top surface of a substrate; and

charge storage regions that are located at each level of the electrically conductive layers, laterally surrounding the semiconductor channel, and vertically spaced from one another.

2. The monolithic three-dimensional memory device of claim 1, further comprising a tunneling dielectric laterally surrounding the semiconductor channel, wherein an inner sidewall of each charge storage region contacts a respective portion of an outer sidewall of the tunneling dielectric.

3. The monolithic three-dimensional memory device of claim 2, further comprising a continuous blocking dielectric layer that contacts each lower silicon oxide material layer, each upper silicon oxide material layer, and each dielectric fill material region, each charge storage region, and the tunneling dielectric.

4. The monolithic three-dimensional memory device of claim 3, wherein the continuous blocking dielectric layer comprises:

a plurality of laterally protruding portions in contact with an outer sidewall of a respective charge storage region; and

a plurality of laterally recessed portions extending between a respective pair of laterally protruding portions and contacting a respective portion of the outer sidewall of the tunneling dielectric.

5. The monolithic three-dimensional memory device of claim 4, wherein each surface of the charge storage regions is in physical contact with the continuous blocking dielectric layer or the tunneling dielectric.

6. The monolithic three-dimensional memory device of claim 4, wherein:

the plurality of laterally recessed regions comprises a silicon oxynitride in which an atomic concentration of nitrogen atoms is grater than 0.1%; and

the plurality of laterally protruding regions comprises a silicon oxide material in which an atomic concentration of nitrogen atoms is less than 100 parts per million.

7. The monolithic three-dimensional memory device of claim 2, further comprising a plurality of vertically spaced apart blocking dielectrics that contact an outer sidewall of a respective charge storage region and contacting an overlying dielectric fill material region and an underlying dielectric fill material region.

8. The monolithic three-dimensional memory device of claim 7, wherein each dielectric fill material region comprises a dielectric material that contacts a respective portion of the outer sidewall of the tunneling dielectric between a vertically neighboring pair of the charge storage regions.

9. The monolithic three-dimensional memory device of claim 8, wherein:

each of the spaced apart blocking dielectrics comprise an annular silicon oxide spacer;

an outer sidewall of each charge storage region contacts an inner sidewall of the annular silicon oxide spacer.

10. The monolithic three-dimensional NAND strong of claim 9, wherein each surface of the charge storage regions contacts a surface the tunneling dielectric, a surface the dielectric material of one of the dielectric fill material regions, or a surface of one of the annular silicon oxide spacers.

11. The monolithic three-dimensional memory device of claim 2, wherein the dielectric fill material region consists of a dielectric material portion having a homogenous composition and does not include any cavity.

12. The monolithic three-dimensional memory device of claim 2, wherein the dielectric fill material region comprises a cavity that is free of a solid material and is encapsulated by a dielectric material.

13. The monolithic three-dimensional memory device of claim 1, wherein each charge storage region has an annular shape, a vertical inner sidewall, and a vertical outer sidewall.

14. The monolithic three-dimensional memory device of claim 1, wherein:

the charge storage regions comprise silicon nitride; and

the semiconductor channel comprises a polycrystalline silicon-containing semiconductor material.

15. The monolithic three-dimensional memory device of claim 1, wherein the dielectric fill material regions are portions of a contiguous dielectric fill material layer that contacts sidewalls of each conductive material layer, each lower silicon oxide layer, and each upper silicon oxide layer within the vertically repeating stack.

16. The monolithic three-dimensional memory device of claim 1, wherein each of the dielectric fill material regions comprises:

a first vertically protruding portion that contacts a sidewall of a respective upper silicon oxide material layer; and

a second vertically protruding portion that contacts a sidewall of a respective lower silicon oxide material layer.

17. The monolithic three-dimensional memory device of claim 1, wherein the unit layer stack further comprises a backside blocking dielectric comprising a dielectric metal oxide and contacting a top surface, a bottom surface, and a sidewall surface of a respective electrically conductive layer.

18. The monolithic three-dimensional memory device of claim 1, wherein:

the monolithic three-dimensional memory device comprises a vertical NAND device located in a device region;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the vertically repeating stack are in electrical contact with the plurality of control gate electrodes and extend from the device region to a contact region including a plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the vertical NAND device.

19. A method of forming a monolithic three-dimensional memory device, comprising:

forming a stack of alternating first material layers and second material layers over a major surface of a substrate, wherein each of the second material layers comprises a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, and the first material layers comprise a material that is different than the first silicon oxide material and the second silicon oxide material;

forming a memory opening through the stack;

forming at least a portion of a memory film over a sidewall of the memory opening;

forming a semiconductor channel in the memory opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the memory opening;

replacing the first material layers with electrically conductive layers; and

replacing at least the first silicon oxide material layers with insulating layers.

20. The method of claim 19, further comprising:

forming a blocking dielectric layer over the sidewall of the memory opening prior to forming the memory film, wherein the memory film comprises a tunneling dielectric and a charge storage layer; and

removing portions of the blocking dielectric layer at each level of the first oxide material layers to form discrete blocking dielectrics that are vertically spaced apart and located at each level of the electrically conductive layers.

21. The method of claim 20, further comprising oxidizing physically exposed portions of the charge storage layer after formation of the discrete blocking dielectrics, wherein:

physically exposed portions of the charge storage layer are converted into respective dielectric oxide portions and are adjoined to the discrete blocking dielectrics to form a continuous blocking dielectric layer; and

the continuous blocking dielectric layer includes all materials of the discrete blocking dielectrics and the dielectric oxide portions and continuously extending vertically through the memory opening.

22. The method of claim 21, wherein the continuous blocking dielectric layer has a vertical compositional modulation in a concentration of nitrogen atoms such that the concentration of nitrogen atoms is at maxima at levels of the insulating layers and is at minima at levels of the electrically conductive layers.

23. The method of claim 21, wherein the continuous blocking dielectric layer comprises:

a plurality of laterally protruding portions in contact with an outer sidewall of a respective remaining portion of the charge storage layer; and

a plurality of laterally recessed portions extending between a respective pair of laterally protruding portions and contacting a respective portion of an outer sidewall of the tunneling dielectric.

24. The method of claim 21, wherein unoxidized portions of the charge storage layer form discrete charge storage regions that are located at each level of the electrically conductive layers, laterally surrounding the semiconductor channel, and vertically spaced apart from one another.

25. The method of claim 20, further comprising removing physically exposed portions of the charge storage layer at each level of the first oxide material layers to form discrete charge storage regions that are vertically spaced apart and located at each level of the electrically conductive layers.

26. The method of claim 25, wherein:

removal of the physically exposed portions of the charge storage layer is performed selective to the discrete blocking dielectrics;

an upper portion and a lower portion of an inner sidewall of each discrete blocking dielectric are physically exposed; and

a middle portion of the inner sidewall of each discrete blocking dielectric contacts an outer sidewall of a respective charge storage region.

27. The method of claim 25, wherein portions of an outer sidewall of the tunneling dielectric are physically exposed at each level from which the first oxide material layers are physically removed.

28. The method of claim 20, wherein:

the charge storage layer comprises silicon nitride;

the second material layers comprise silicon nitride; and

the blocking dielectric layer comprises silicon oxide.

29. The method of claim 19, further comprising:

removing the first silicon oxide material layers selective to the second silicon oxide material layers to form backside recesses; and

depositing the insulating layers having a dielectric constant of 3.9 or less in the backside recesses.

30. The method of claim 29, wherein the insulating layers fill each of the backside recesses without a cavity therein.

31. The method of claim 29, wherein the insulating layers form a cavity that is free of any solid material within each level of the backside recesses.

32. The method of claim 19, further comprising:

forming backside recesses by removing the first material layers; and

forming a backside blocking dielectric comprising a dielectric metal oxide within each of the backside recesses, wherein each electrically conductive layer is formed within a remaining volume of a respective backside recess and directly on a respective backside blocking dielectric.

33. The method of claim 19, further comprising removing portions of the charge storage layer at each level of the first silicon oxide material layers, wherein remaining portions of the charge storage layer constitute discrete charge storage regions located at each level of the electrically conductive layers.

34. The method of claim 19, wherein:

the monolithic three-dimensional memory device comprises a vertical NAND device located in a device region;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the device region comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;

the electrically conductive layers in the vertically repeating stack are in electrical contact with the plurality of control gate electrodes and extend from the device region to a contact region including a plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the vertical NAND device.