GAN TRANSISTORS WITH POLYSILICON LAYERS USED FOR CREATING ADDITIONAL COMPONENTS

• US 20160086980A1
• Filed: 12/04/2015
• Published: 03/24/2016
• Est. Priority Date: 07/29/2013
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: Cao, Jianjun, Beach, Robert, Lidow, Alexander, Nakata, Alana, Zhao, Guangyuan, Ma, Yanping, Strittmatter, Robert, De Rooij, Michael A., Zhou, Chunhua, Kolluri, Seshadri, Chiang, Ming-Kun, Cao, Jiali, Jauhar, Agus, Liu, Fang-Chang
• Granted Patent: US 9,837,438 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/7605 between components manufactured in an active substrate comprising AIII BV compounds
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42384 : for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66765 : Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Claims

1. A method of manufacturing an integrated circuit, the method comprising:

forming a gate structure for an enhancement mode device;

depositing a first insulating layer over the gate structure;

depositing a polysilicon layer on the first insulating layer;

doping the polysilicon layer to form at least one p-type region in the polysilicon layer;

depositing a second insulating layer on the polysilicon layer;

forming a metal layer on the second insulating layer that is coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the second insulating layer.

2. The method according to claim 1, further comprising:

depositing a channel layer over at least one buffer layer; and

depositing a barrier layer over the channel layer.

3. The method according to claim 2, wherein the step of forming the gate structure comprises:

depositing a p-type GaN layer over the barrier layer;

depositing a gate metal on the p-type GaN layer;

forming a photoresist over the gate metal; and

etching the gate metal and the p-type GaN layer.

4. The method according to claim 3, further comprising:

etching the first insulating layer to form a pair of contact windows in the insulating material on opposite sides of the gate structure; and

forming a source metal and a drain metal in the pair of contact windows, respectively.

5. The method according to claim 1, wherein the step of doping the polysilicon layer further comprises doping the polysilicon layer to form at least one n-type region in the polysilicon layer.

6. The method according to claim 5, wherein the step of forming a metal layer on the second insulating layer comprises forming a first metal interconnect electrically coupled to the at least one n-type region of the polysilicon layer and a second metal interconnect electrical coupled to the at least one p-type region of the polysilicon layer by respective vias in the second insulating layer.

7. The method according to claim 6, further comprising:

depositing a third insulating layer on the first metal interconnect and the second interconnect;

forming a plurality of vias in the third insulating layer; and

forming a pair of metal contacts on the third insulating layer and electrically coupled to the plurality of vias.

8. The method according to claim 6, further comprising:

forming an additional polysilicon layer; and

forming a third insulating layer on the additional polysilicon layer.

9. The method according to claim 8, further comprising:

forming at least one additional via in the third insulating layer and electrically coupled to the additional polysilicon layer; and

forming a metal contact on the third insulating layer and electrically coupled to the additional polysilicon layer by the at least one additional via.

10. The method according to claim 6, wherein the step of doping the polysilicon layer further comprises leaving at least one region of the polysilicon layer undoped.

11. The method according to claim 10, wherein the undoped region of the polysilicon layer is electrically connected to the second metal interconnect by an additional via.

12. A method of manufacturing an integrated circuit, the method comprising:

depositing a channel layer over at least one buffer layer;

depositing a barrier layer over the channel layer, such that a two dimensional electron gas (2DEG) region is formed at an interface between the channel layer and the barrier layer;

forming an isolation region in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region;

forming a gate structure for an enhancement mode device over the first portion of the 2DEG region;

depositing a first insulating layer over the gate structure;

forming a back gate over the second portion of the 2DEG region;

depositing a second insulating layer over the back gate;

depositing a polysilicon layer on the second insulating layer and etching the polysilicon layer, such that at least a portion of the etched polysilicon layer is disposed over the back gate;

doping the etched polysilicon layer to form at least one p-type region in the polysilicon layer;

depositing a third insulating layer on the etched polysilicon layer; and

forming at least one metal interconnect layer on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer.

13. The method according to claim 12, wherein the step of forming the back gate over the second portion of the 2DEG region comprises depositing a gate metal on the first insulating layer and etching the gate metal, such that the etched gate metal is disposed over the second portion of the 2DEG region.

14. The method according to claim 13, wherein the step of etching the gate metal comprises etching the gate metal and the first insulating layer to form a pair of contact windows extending to the barrier layer on opposite sides of the gate structure.

15. The method according to claim 14, further comprising forming a source metal and a drain metal in the pair of contact windows, respectively, wherein at least a portion of the source metal and a portion of the drain metal are each disposed over the gate metal.

16. The method according to claim 15, wherein the step of depositing the second insulating layer further comprises depositing the second insulating layer on the source metal and the drain metal.

17. The method according to claim 12, wherein the steps of forming the gate structure over the first portion of the 2DEG region and forming the back gate over the second portion of the 2DEG region comprises:

depositing a p-type GaN layer over the barrier layer;

depositing a gate metal on the p-type GaN layer;

forming a patterned photoresist on a first portion of the gate metal disposed over the first portion of the 2DEG region and on a second portion of the gate metal disposed over the second portion of the 2DEG region; and

etching the gate metal and the p-type GaN layer.

18. The method according to claim 12, wherein the step of forming the isolation region comprises one of ion implantation in or etching of the barrier layer and the channel layer.

19. The method according to claim 12, wherein the step of doping the polysilicon layer further comprises doping the polysilicon layer to form at least one n-type region in the polysilicon layer.

20. The method according to claim 19, wherein the step of doping the polysilicon layer further comprises forming either a second n-type region or a second p-type region, such that the doped polysilicon layer comprises either a PNP layer or an NPN layer as a source, a gate and a drain of an FET device.

21. An integrated circuit comprising:

a channel layer disposed over at least one buffer layer;

a barrier layer disposed over the channel layer, with a two dimensional electron gas (2DEG) region formed at an interface between the channel layer and the barrier layer;

an isolation region disposed in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region;

a gate structure for an enhancement mode device disposed over the first portion of the 2DEG region;

a first insulating layer disposed over the gate structure;

a back gate disposed over the second portion of the 2DEG region;

a second insulating layer disposed over the back gate;

a polysilicon layer disposed on the second insulating layer and over the back gate, the polysilicon layer including at least one p-type region;

a third insulating layer disposed on the etched polysilicon layer; and

at least one metal interconnect layer disposed on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer.

22. The integrated circuit according to claim 21, wherein the back gate over the second portion of the 2DEG region is disposed on the first insulating layer.

23. The integrated circuit according to claim 22, further comprising a pair of contact windows extending through the gate metal and the first insulating layer to to the barrier layer on opposite sides of the gate structure.

24. The integrated circuit according to claim 23, further comprising a source metal and a drain metal disposed in the pair of contact windows, respectively, wherein at least a portion of the source metal and a portion of the drain metal are each disposed over the gate metal.

25. The integrated circuit according to claim 21, wherein the second insulating layer is disposed on the source metal and the drain metal.

26. The integrated circuit according to claim 22, wherein the gate structure and the back gate each comprise a p-type GaN layer disposed over the barrier layer and a gate metal disposed on the p-type GaN layer.

27. The integrated circuit according to claim 21, wherein the polysilicon layer further comprises at least one n-type region.

28. The integrated circuit according to claim 27, wherein the polysilicon layer further comprises either a second n-type region or a second p-type region, such that the doped polysilicon layer comprises either a PNP layer or an NPN layer as a source, a gate and a drain of an FET device.