SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20160087045A1
• Filed: 07/30/2015
• Published: 03/24/2016
• Est. Priority Date: 09/19/2014
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SHIMIZU, Tatsuo
• Granted Patent: US 9,893,153 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/3211 Nitridation of silicon-containing layers
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device according to an embodiment includes a SiC layer, a gate electrode, a gate insulating film provided between the SiC layer and the gate electrode, a first region provided between the SiC layer and the gate insulating film, and a second region provided in the SiC layer. The first region contains at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine). The second region provided adjacent to the first region, and the second region has a higher oxygen concentration than a concentration of the at least one element.

Claims

1. A semiconductor device comprising:

a SiC layer;

a gate electrode;

a gate insulating film provided between the SiC layer and the gate electrode;

a first region provided between the SiC layer and the gate insulating film, the first region containing at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine); and

a second region provided in the SiC layer, the second region provided adjacent to the first region, the second region having a higher oxygen concentration than a concentration of the at least one element.

2. The device according to claim 1, wherein the SiC layer is of a p-type.

3. The device according to claim 1, wherein a distance between a boundary between the first region and the second region, and a peak position of the concentration of the at least one element in the first region is 5 nm or shorter.

4. The device according to claim 1, wherein the oxygen concentration in the second region is not lower than 1×

10¹⁶ cm<sup>−

3</sup> and not higher than 1×

10²¹ cm<sup>−

3</sup>.

5. The device according to claim 1, wherein a Si—

O—

Si bond exists in the second region.

6. The device according to claim 1, wherein carbon site in a SiC lattice is occupied by oxygen in the second region.

7. The device according to claim 1, wherein a peak concentration of the at least one element in the first region is not lower than 1×

10¹⁸ cm<sup>−

3</sup> and not higher than 1×

10²³ cm<sup>−

3</sup>.

8. The device according to claim 1, wherein the gate insulating film is a silicon oxide film.

9. A semiconductor device manufacturing method comprising:

forming a second region containing oxygen in a SiC layer by performing a first heat treatment in an oxygen-containing atmosphere under a condition that an amount of oxidized SiC becomes smaller than 1 nm;

forming a first region on the second region after the formation of the second region, the first region containing at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine);

depositing a gate insulating film on the SiC layer; and

forming a gate electrode on the gate insulating film.

10. The method according to claim 9, further comprising

forming a thermally-oxidized film of 5 nm or smaller in thickness in the SiC layer prior to the formation of the second region.

11. The method according to claim 9, wherein the SiC layer is of a p-type.

12. The method according to claim 9, wherein the first region is formed through nitriding of the SiC layer.

13. The method according to claim 9, wherein temperature in the first heat treatment is 900°

C. or lower.

14. The method according to claim 9, further comprising,

performing a second heat treatment after the formation of the first region, the second heat treatment being performed in an oxygen-containing atmosphere under a condition that an amount of oxidized SiC becomes smaller than 1 nm.

15. A semiconductor device manufacturing method comprising:

forming a gate insulating film by thermally oxidizing a SiC layer;

forming a second region in the SiC layer after the formation of the gate insulating film, the second region containing oxygen, the second region being formed by performing a first heat treatment in an oxygen-containing atmosphere under a condition that an amount of oxidized SiC becomes smaller than 1 nm;

forming a first region between the gate insulating film and the second region, the first region containing at least one element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), H (hydrogen), D (deuterium), and F (fluorine); and

forming a gate electrode on the gate insulating film.

16. The method according to claim 15, wherein the SiC layer is of a p-type.

17. The method according to claim 15, wherein the first region is formed through nitriding of the SiC layer.

18. The method according to claim 15, wherein temperature in the first heat treatment is 900°

C. or lower.

19. The method according to claim 15, further comprising,

performing a second heat treatment after the formation of the first region, the second heat treatment being performed in an oxygen-containing atmosphere under a condition that an amount of oxidized SiC becomes smaller than 1 nm.