SPLIT GATE MEMORY DEVICE FOR IMPROVED ERASE SPEED

• US 20160087056A1
• Filed: 09/23/2014
• Published: 03/24/2016
• Est. Priority Date: 09/23/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chang-Ming, Yang, Tsung-Hsueh, Chen, Sheng-Chieh, Liu, Shih-Chang
• Granted Patent: US 9,391,151 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.

Claims

1. A memory device, comprising:

a semiconductor substrate comprising a source region and drain region, which are laterally separated from one another by a channel region;

a floating gate arranged over the channel region, wherein a first gate dielectric separates the floating gate from the channel region;

a control gate arranged over the floating gate, wherein a second gate dielectric separates the control gate from the floating gate;

an erase gate arranged adjacent the control and floating gates, and over the source region; and

a source-facing sidewall spacer arranged between the control and erase gates along a source-facing sidewall of the control gate, and over a floating gate upper surface, wherein the floating gate upper surface extends horizontally past the source-facing sidewall spacer to form a floating gate ledge adjacent the erase gate.

2. The memory device of claim 1, wherein the floating gate ledge extends along a length of the source-facing sidewall of the control gate.

3. The memory device of claim 1, wherein the floating gate has an asymmetric shape about a vertical axis that bisects the floating gate upper surface.

4. The memory device of claim 3,

wherein a drain-facing floating gate sidewall forms a substantially planar vertical surface;

and

wherein a source-facing floating gate sidewall forms a concave surface, which tapers down from the floating gate ledge towards a neck region within the floating gate, wherein the neck region is narrower than the floating gate upper surface.

5. The memory device of claim 4, wherein the neck region is narrower than a floating gate lower surface.

6. The memory device of claim 1, further comprising:

a tunneling dielectric layer that extends along a source-facing floating gate sidewall to separate the erase gate from the floating gate;

wherein a horizontal surface of the tunneling dielectric layer arranged over the floating gate upper surface forms a tunneling dielectric ledge that is arranged over the floating gate ledge.

7. The memory device of claim 6, wherein the tunneling dielectric layer has a uniform thickness between the erase gate and the floating gate.

8. The memory device of claim 1, further comprising a drain-facing sidewall spacer arranged along a drain-facing sidewall of the control gate and over the floating gate upper surface, the drain-facing sidewall spacer comprising:

a first spacer dielectric layer comprising a first horizontal portion that extends over the floating gate upper surface, and a first vertical portion that extends along the drain-facing sidewall of the control gate;

a spacer nitride layer comprising a second horizontal portion that extends over the first horizontal portion of the first spacer dielectric layer, and a second vertical portion that extends along the first vertical portion of the first spacer dielectric layer; and

a second spacer dielectric layer arranged over the second horizontal portion of the spacer nitride layer that extends along the second vertical portion of the spacer nitride layer.

9. The memory device of claim 8, further comprising:

a memory gate arranged over the channel region;

a gap oxide that isolates the drain-facing sidewall spacer from the memory gate; and

a vertical nitride layer that isolates the drain-facing sidewall spacer from the gap oxide.

10. The memory device of claim 1, further comprising an oxide-nitride-oxide (ONO) layer arranged between the floating gate and the control gate, the ONO layer comprising a first gate dielectric layer arranged over the floating gate, a nitride layer formed over the first gate dielectric layer, and a second dielectric layer arranged over the nitride layer.

11. An integrated circuit containing a memory device, the memory device comprising:

a semiconductor substrate comprising a source region and drain region, which are laterally separated from one another by a channel region;

a gate stack arranged over the channel region, the gate stack comprising;

a floating gate arranged over the channel region, wherein a first gate dielectric separates the floating gate from the channel region; and

a control gate arranged over the floating gate, wherein a second gate dielectric separates the control gate from the floating gate, and wherein the control gate is narrower than the floating gate; and

a source-facing sidewall spacer and a drain-facing sidewall spacer, which are formed along opposite vertical sidewalls of the control gate and over a floating gate upper surface, wherein the floating gate upper surface extends horizontally past the source-facing sidewall spacer, thereby forming a floating gate ledge adjacent the source region.

12. The integrated circuit of claim 11, wherein a source-facing floating gate sidewall forms a concave surface, which tapers down from the floating gate ledge towards a neck region within the floating gate, wherein the neck region is narrower than the floating gate upper surface and a floating gate lower surface.

13. The integrated circuit of claim 11, further comprising:

a tunneling dielectric layer that extends along the source-facing sidewall spacer of the floating gate;

wherein a horizontal surface of the tunneling dielectric layer arranged over the floating gate upper surface forms a tunneling dielectric ledge arranged over the floating gate ledge.

14. The integrated circuit of claim 13, further comprising an erase gate arranged over the source region, wherein the erase gate is separated from the gate stack by the tunneling dielectric layer.

15. The integrated circuit of claim 11, further comprising:

a gap oxide arranged vertically along the drain-facing sidewall spacer;

a memory gate arranged over the channel region, and separated from the gate stack by the gap oxide; and

a vertical nitride layer that isolates the drain-facing sidewall spacer from the gap oxide.

16. The integrated circuit of claim 11, further comprising a second memory device, which is a mirror image of the memory device, and which shares the source region with the memory device.

17-20. -20. (canceled)

21. A memory device, comprising:

a semiconductor substrate comprising a source region and drain region, which are laterally separated from one another by a channel region;

a floating gate arranged over the channel region, wherein a first gate dielectric separates the floating gate from the channel region;

a control gate arranged over the floating gate, wherein a second gate dielectric separates the control gate from the floating gate;

an erase gate arranged adjacent the control and floating gates, and over the source region;

a drain-facing sidewall spacer that laterally contacts the control gate along a drain-facing sidewall of the control gate, wherein the drain-facing sidewall spacer is arranged over an upper surface of the floating gate; and

a vertical nitride layer arranged over an upper surface of the floating gate and is spaced apart from the drain-facing sidewall by the drain-facing sidewall spacer.

22. The memory device of claim 21, further comprising:

a source-facing sidewall spacer arranged between the control and erase gates along a source-facing sidewall of the control gate, and over the upper surface of the floating gate, wherein the upper surface of the floating gate extends horizontally past the source-facing sidewall spacer to form a floating gate ledge adjacent the erase gate.

23. The memory device of claim 22, wherein the floating gate ledge extends along a length of the source-facing sidewall of the control gate.

24. The memory device of claim 21, wherein the floating gate has an asymmetric shape about a vertical axis that bisects the floating gate upper surface.