TRANSIENT-TRIGGERED DC VOLTAGE-SUSTAINED POWER-RAIL ESD CLAMP CIRCUIT

• US 20160087429A1
• Filed: 03/10/2014
• Published: 03/24/2016
• Est. Priority Date: 05/09/2013
• Status: Active Grant

• Current Assignee: Peking University
• Original Assignee: Peking University
• Inventors: WANG, Yuan, LU, Guangyi, CAO, Jian, ZHANG, Xing
• Granted Patent: US 10,096,994 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H02H 9/04 responsive to excess voltage lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

A transient-triggered DC voltage-sustained power-rail ESD clamp circuit comprises: a transient-triggered module, a DC voltage-triggered module and a discharge device, wherein the transient-triggered module is connected with the DC voltage-triggered module and the discharge device respectively. When an ESD event is approaching, the ESD protection circuit can be turned on well and quickly, and can effectively avoid the problems of erroneous triggering and latching-up caused by quick power-on and high-frequency noise at the same time.

Claims

1. A transient-triggered DC voltage-sustained power-rail ESD clamp circuit, comprising a transient-triggered module, a DC voltage-triggered module and a discharge device;

the transient-triggered module is connected with the discharge device, and used for judging whether a obtained pulse meets transient judgement condition of an ESD event according to rise time of the pulse, and if so, then a first response signal is sent to the discharge device, and the first response signal is used for turning on the discharge device;

the DC voltage-triggered module is connected with the transient-triggered module, and used for judging whether the pulse meets DC voltage judgement condition of the ESD event according to amplitude of the pulse, and if so, then a second response signal is sent to the transient-triggered module, and the transient-triggered module controls the discharge device to keep in a turn-on state according to the second response signal;

the discharge device is used for discharging static charges brought by the pulse.

2. The transient-triggered DC voltage-sustained power-rail ESD clamp circuit according to claim 1, characterized in that the transient-triggered module comprises:

a PMOS transistor M_p2, NMOS transistors M_n2 and M_fb2, a resistor R₂ and a capacitor C, wherein a gate electrode of the PMOS transistor M_p2 is connected with that of the NMOS transistor M_n2, a source electrode of the NMOS transistor M_n2 is grounded, a drain electrode of the NMOS transistor M_n2 is connected with that of the PMOS transistor M_p2, a source electrode of the PMOS transistor M_p2 is connected with a power pin V_DD of the transient-triggered DC voltage-sustained power-rail ESD clamp circuit, a source electrode of the NMOS transistor M_fb2 is grounded, a drain electrode of the NMOS transistor M_fb2 is connected with a gate electrode of the PMOS transistor M_p2, one end of the resistor R₂ is connected with the power pin V_DD of transient-triggered DC voltage-sustained power-rail ESD clamp circuit, the other end of the resistor R₂ is connected with the gate electrode of the PMOS transistor M_p2, one end of the capacitor C is connected with the gate electrode of the PMOS transistor M_p2, and the other end of the capacitor C is grounded.

3. The transient-triggered DC voltage-sustained power-rail ESD clamp circuit according to claim 2, characterized in that the DC voltage-triggered module comprises:

a PMOS transistor M_p1, NMOS transistors M_n1, M_fb1 and M_nc, and a resistor R₁, wherein a gate electrode of the PMOS transistor M_p1 is connected with that of the NMOS transistor M_n1, a source electrode of the NMOS transistor M_n1 is grounded, a drain electrode of the NMOS transistor M_n1 is connected with that of the PMOS transistor M_p1, a source electrode of the PMOS transistor M_p1 is connected with the power pin V_DD of the transient-triggered DC voltage-sustained power-rail ESD clamp circuit, a gate electrode of the NMOS transistor M_fb1 is connected with the drain electrode of the PMOS transistor M_p1, the gate electrode of the NMOS transistor M_fb1 is also connected with that of the NMOS transistor M_fb2, the source electrode of the NMOS transistor M_fb1 is grounded, a drain electrode of the NMOS transistor M_fb1 is connected with a gate electrode of the PMOS transistor M_p1, a gate electrode of the NMOS transistor M_nc is connected with the gate electrode of the PMOS transistor M_p1, a source electrode of the NMOS transistor M_nc is grounded, a drain electrode of the NMOS transistor M_nc is connected with the gate electrode thereof, one end of the resistor R₁ is connected with the power pin V_DD of the transient-triggered DC voltage-sustained power-rail ESD clamp circuit, and the other end of the resistor R₁ is connected with the gate electrode of the NMOS transistor M_nc.

4. The transient-triggered DC voltage-sustained power-rail ESD clamp circuit according to claim 2, characterized in that the discharge device is an NMOS transistor M_big, the gate electrode of the NMOS transistor M_big is connected with the drain electrode of the PMOS transistor M_p2, the source electrode of the NMOS transistor M_big is grounded, and the drain electrode of the NMOS transistor M_big is connected with the power pin V_DD of the transient-triggered DC voltage-sustained power-rail ESD clamp circuit.

5. The transient-triggered DC voltage-sustained power-rail ESD clamp circuit according to claim 3, characterized in that the discharge device is an NMOS transistor M_big, the gate electrode of the NMOS transistor M_big is connected with the drain electrode of the PMOS transistor M_p2, the source electrode of the NMOS transistor M_big is grounded, and the drain electrode of the NMOS transistor M_big is connected with the power pin V_DD of the transient-triggered DC voltage-sustained power-rail ESD clamp circuit.