RECEIVER CIRCUIT

• US 20160087479A1
• Filed: 09/22/2014
• Published: 03/24/2016
• Est. Priority Date: 09/22/2014
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Inventors: MCFARTHING, Anthony Lawrence
• Granted Patent: US 9,906,064 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H02J 50/20 using microwaves or radio frequency waves
• CPC Class Codes: H02J 50/40 using two or more transmitting or receiving devices H02J50/50 takes precedence
• CPC Class Codes: H04B 5/0037 for power transfer
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer

Abstract

A receiver circuit and a device incorporating a receiver circuit are described, including a receiver circuit comprising a first rectifier arranged to receive a signal from an antenna, a second rectifier arranged to receive the signal from the antenna, and a first depletion mode NMOS transistor switch connected between the first rectifier and a first output of the receiver circuit, wherein a drain of the first transistor switch is connected to a first output of the first rectifier, a source of the first transistor switch comprises the first output of the receiver circuit, and a gate of the first transistor switch is arranged to receive a voltage based on an output of the second rectifier, such that the transistor switch is opened when a level of the signal from the antenna exceeds a predetermined level.

Claims

1. A receiver circuit comprising:

a first rectifier arranged to receive a signal from an antenna;

a second rectifier arranged to receive the signal from the antenna;

a first depletion mode NMOS transistor switch connected between the first rectifier and a first output of the receiver circuit, wherein a drain of the first transistor switch is connected to a first output of the first rectifier, a source of the first transistor switch comprises the first output of the receiver circuit, and a gate of the first transistor switch is arranged to receive a voltage based on an output of the second rectifier, such that the transistor switch is opened when a level of the signal from the antenna exceeds a predetermined level.

2. The receiver circuit of claim 1, further comprising a circuit for supplying a gate voltage to the gate of the first transistor switch based on the output of the second rectifier.

3. The receiver circuit of claim 2, wherein the circuit for supplying the gate voltage comprises at least one of a filter and a potential divider arranged between the output of the second rectifier and the gate of the first transistor switch.

4. The receiver circuit of claim 1, wherein the first rectifier is a full-wave rectifier.

5. The receiver circuit of claim 4, wherein the first rectifier comprises a second output, and wherein the receiver circuit further comprises a second depletion mode NMOS transistor switch connected between the first rectifier and a second output of the receiver circuit, wherein a drain of the second transistor switch is connected to the second output of the first rectifier, a source of the first transistor switch comprises the second output of the receiver circuit, and a gate of the first transistor switch is arranged to receive a voltage based on an output of the second rectifier, such that the transistor switch is opened when a level of the signal from the antenna exceeds a predetermined level.

6. The receiver circuit of claim 5, wherein the signal from the antenna is a differential signal comprising a first antenna signal and a second antenna signal, and wherein the first rectifier comprises a first diode connected between a first node arranged to receive the first antenna signal and the drain of the first transistor, and a second diode connected between a second node arranged to receive the second antenna signal and the drain of the second transistor.

7. The receiver circuit of claim 6, wherein the second rectifier comprises a third diode connected between the first node and the output of the second rectifier, and a fourth diode connected between the second node and the output of the second rectifier, wherein the first node is connected to an anode of the first diode and a cathode of the third diode, and the second node is connected to the anode of the second diode and the cathode of the fourth diode.

8. The receiver circuit of claim 5, wherein the gate of the first transistor is coupled to the gate of the second transistor switch.

9. The receiver circuit of claim 1, wherein the second rectifier is a full-wave rectifier.

10. The receiver circuit of claim 1, wherein the first rectifier provides a substantially positive voltage relative to a ground voltage and the second rectifier provides a substantially negative voltage relative to the ground voltage.

11. The receiver circuit of claim 1, wherein the first output of the receiver circuit is connected to a communications circuit.

12. The receiver circuit of claim 11, wherein the communications circuit is at least one of a NFC communications circuit and a RFID communications circuit.

13. The receiver circuit of claim 1, wherein the voltage based on an output of the second rectifier is arranged such that the transistor switch is opened when the signal received by the antenna is a wireless charging signal.

14. A device, comprising:

an antenna;

a receiver circuit; and

a communications circuit;

wherein the receiver circuit comprises;

a first rectifier arranged to receive a signal from an antenna;

a second rectifier arranged to receive the signal from the antenna;

a first depletion mode NMOS transistor switch connected between the first rectifier and a first output of the receiver circuit, wherein a drain of the first transistor switch is connected to a first output of the first rectifier, a source of the first transistor switch comprises the first output of the receiver circuit, and a gate of the first transistor switch is arranged to receive a voltage based on an output of the second rectifier, such that the transistor switch is opened when a level of the signal from the antenna exceeds a predetermined level.

15. The device of claim 14, wherein the communications circuit is at least one of a NFC communications circuit and a RFID communications circuit.

16. The device of claim 14, wherein the voltage based on an output of the second rectifier is arranged such that the transistor switch is opened when the signal received by the antenna is a wireless charging signal.