Output Buffer, and Source Driver and Display Device Including the Same

• US 20160087627A1
• Filed: 06/09/2015
• Published: 03/24/2016
• Est. Priority Date: 09/22/2014
• Status: Active Grant

• Current Assignee: DB Globalchip Company Limited
• Original Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Inventors: JANG, Dae Joong
• Granted Patent: US 9,654,100 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

Disclosed is an output buffer. The output buffer includes a first amplifier configured to amplify an input signal, and output first to fourth amplified signals according to results of the amplification, a first transistor to receive the first amplified signal, a second transistor to receive the second amplified signal, a third transistor to receive the third amplified signal, a fourth transistor to receive the fourth amplified signal, a first node, connected to drains of the first and second transistors, a second node, connected to drains of the third and fourth transistors, an output node connected to the first and second nodes, and a first controller configured to selectively supply a control voltage to the gates of the first to fourth transistors in response to a control signal.

Claims

1. An output buffer comprising:

a first amplifier configured to amplify an input signal and output first to fourth amplified signals;

a first transistor comprising a first drain, a first gate configured to receive the first amplified signal, and a first source;

a second transistor comprising a second drain connected to the first drain at a first node, a second gate configured to receive the second amplified signal, and a second source;

a third transistor comprising a third drain, a third gate configured to receive the third amplified signal, and a third source connected to the second source;

a fourth transistor comprising a fourth drain connected to the third drain at a second node, a fourth gate configured to receive the fourth amplified signal, and a fourth source;

an output node connected to the first and second nodes; and

a first controller configured to selectively supply a control voltage to the first to fourth gates in response to a control signal.

2. The output buffer according to claim 1, wherein a first supply voltage is supplied to the fourth source, a second supply voltage higher than the first supply voltage is supplied to the second source and the third source, and a third supply voltage higher than the second supply voltage is supplied to the first source.

3. The output buffer according to claim 1, wherein the first and third transistors have a first conduction type, the second and fourth transistors have a second conduction type, and the first conduction type is opposite or complementary to the second conduction type.

4. The output buffer according to claim 1, wherein the first controller disconnects the control voltage to the third and fourth gates when the control voltage is supplied to the first and second gates.

5. The output buffer according to claim 4, wherein:

the control voltage comprises a first supply voltage and a third supply voltage higher than the first supply voltage; and

the first controller supplies one of the first and third supply voltages to one of the first and second gates or one of the third and fourth gates, and supplies the other of the first and third supply voltages to the other of the first and second gates and/or the other of the third and fourth gates.

6. The output buffer according to claim 1, wherein the first controller is configured to supply the control voltage to the first and second gates and disconnect the control voltage from the third and fourth gates, or supply the control voltage to the third and fourth gates and disconnect the control voltage from the first and second gates.

7. The output buffer according to claim 6, wherein the first controller comprises first and second switches having a first conduction type, and third and fourth switches having a second conduction type, the first conduction type being opposite or complementary to the second conduction type.

8. The output buffer according to claim 1, further comprising:

a switching unit configured to supply the amplified signals to the first to fourth gates or disconnect the amplified signals from the first to fourth gates in response to the control signal.

9. The output buffer according to claim 8, wherein the switching unit is configured to supply the amplified signals to the first and second gates and disconnect the amplified signals from the third and fourth gates when the control signal has a first logic level, and supply the amplified signals to the third and fourth gates and disconnect the amplified signals from the first and second gates when the control signal has a second logic level.

10. The output buffer according to claim 9, wherein the switching unit comprises fifth and sixth switches having a second conduction type, and seventh and eighth switches having a first conduction type, the second conduction type being opposite or complementary to the first conduction type.

11. The output buffer according to claim 1, wherein the first amplifier supplies the amplified signals to the first to fourth gates or disconnects the amplified signals from the first to fourth gates in response to the control signal.

12. The output buffer according to claim 2, further comprising:

a second controller configured to supply a first leakage cut-off control voltage to a body or bulk of the second transistor and a second leakage cut-off control voltage to a body or bulk of the third transistor.

13. The output buffer according to claim 12, wherein the first leakage cut-off control voltage is supplied to the body or bulk of the second transistor, or the second leakage cut-off control voltage is supplied to the body or bulk of the third transistor, in response to the control signal.

14. The output buffer according to claim 13, wherein the first leakage cut-off control voltage is higher than the third supply voltage, and the second leakage cut-off control voltage is lower than the first supply voltage.

15. The output buffer according to claim 13, wherein the first leakage cut-off control voltage is one of the first and second supply voltages, and the second leakage cut-off control voltage is one of the second and third supply voltages.

16. The output buffer according to claim 2, wherein a first leakage cut-off control voltage lower than the first supply voltage is supplied to a body or bulk of the second transistor, and a second leakage cut-off control voltage higher than the third supply voltage is supplied to a body or bulk of the third transistor.

17. The output buffer according to claim 1, wherein the first amplifier comprises a rail-to-rail amplifier.

18. A source driver comprising:

a latch unit configured to store data;

a level shifter configured to shift a voltage level of the data from the latch unit;

a digital-to-analog converter configured to convert an output from the level shifter to an analog signal; and

the output buffer of claim 1, configured to amplify the analog signal, and output the amplified signal.

19. A display device comprising:

a display panel comprising gate lines in rows and source lines in intersecting columns to form a matrix, and pixels each connected to one of the gate lines and one of the source lines at an intersection thereof;

a plurality of the source drivers of claim 18, configured to drive the source lines; and

a timing controller configured to supply a control signal to each of the source drivers.