Apparatus and Method for Digital to Analog Conversion with Current Mirror Amplification

• US 20160087645A1
• Filed: 12/01/2015
• Published: 03/24/2016
• Est. Priority Date: 02/05/2014
• Status: Active Grant

• Current Assignee: Innophase, Inc.
• Original Assignee: Innophase, Inc.
• Inventors: Zhang, Xuejun, Xu, Yang
• Granted Patent: US 9,438,267 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/625 wherein it is irrelevant whether the variable actually regulated is ac or dc
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H03F 3/04 with semiconductor devices only
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/0854 of quantisation noise
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals
• CPC Class Codes: H03M 3/50 Digital/analogue converters using delta-sigma modulation as an intermediate step digital delta-sigma modulators per se H03M7/3004

Abstract

A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.

Claims

1. A method comprising:

generating a varying current signal that is proportional to a varying input signal, at a current-generating circuit;

generating a bias current, at a bias current source;

driving a mirror input transistor of a current mirror with the bias current and the varying current signal;

generating a corresponding varying voltage signal at a control terminal of the mirror input transistor;

limiting a bandwidth of the varying voltage signal with a signal shaping filter that is interposed between the mirror input transistor and an output mirror transistor of the current mirror;

generating a band-limited varying current signal and a mirrored bias current, at the output mirror transistor; and

, reducing the mirrored bias current, at a mirrored bias current reduction circuit that is connected to the output mirror transistor.

2. The method of claim 1 wherein the mirrored bias current reduction circuit is a voltage level shifter interposed between the input transistor and the output mirror transistor to provide a voltage offset.

3. The method of claim 2 wherein the voltage level shifter comprises an offset current source and an offset resistor interposed between the mirror input transistor and the output mirror transistor.

4. The method of claim 1 wherein the mirrored bias current reduction circuit is a current source configured to provide a bias current to the output mirror transistor.

5. The method of claim 1 wherein the current-generating circuit is one or more current source transistors configured to receive the varying input signal.

6. The method of claim 1 wherein the current-generating circuit, the current mirror, the signal shaping filter and the mirrored bias current reduction circuit are differential signal circuits.

7. The method of claim 1 wherein the current-generating circuit, the current mirror, the signal shaping filter and the mirrored bias current reduction circuit are single-ended signal circuits.

8. The method of claim 1 wherein the varying input signal is a binary signal.

9. The method of claim 1 wherein the varying input signal is a serial stream of single bit data.

10. The method of claim 1 wherein the varying input signal is a multi-bit binary signal.

11. The method of claim 10 wherein the current-generating circuit is a plurality of current source transistors, each of the current source transistors of the plurality being configured to generate an amount of current corresponding to a bit position of the multi-bit binary signal.

12. The method of claim 11 wherein the output mirror transistor is larger than the input transistor to provide current amplification.

13. The method of claim 1 wherein the signal-shaping filter is configured to substantially reduce quantization noise associated with the varying voltage signal.

14. The method of claim 1 wherein the varying input signal is a digital baseband signal.

15. The method of claim 1 further comprising switching the band-limited varying current signal at a mixer.

16. The method of claim 15 wherein the mixer is switched by a carrier signal.

17. A method comprising:

receiving, at a sigma-delta converter, a first binary baseband signal having a first number of bits and an associated first sample rate;

generating, at the sigma-delta converter, a second binary signal having (i) a second number of bits, the second number of bits being less than the first number of bits and (ii) an associated second sampling rate, the second sampling rate being greater than the first sampling rate;

generating, at a current source, a signal current in response to the second binary signal; and

,

driving an input transistor of a current mirror signal amplifier with the signal current to produce a varying voltage signal;

passing the varying voltage signal through a digital-to-analog reconstruction filter interposed between the input transistor and an output current mirror transistor of the current mirror signal amplifier; and

,

outputting an amplified signal current, at the output current mirror transistor.

18. The method of claim 17 wherein the digital-to-analog reconstruction filter is a two-pole RC filter.

19. The method of claim 17 further comprising providing an input bias current to the input transistor, via a bias circuit.

20. The method of claim 19 further comprising reducing a mirrored bias current, at a mirrored bias current reduction circuit that is connected to the output mirror transistor.

21. The method of claim 20 wherein the mirrored bias current reduction circuit is a current source configured to provide a bias current to the output mirror transistor.

22. The method of claim 19 further comprising reducing a mirrored bias current via a voltage offset circuit interposed between the input transistor and the output current mirror transistor.

23. The method of claim 17 further comprising switching the band-limited varying current signal, at a mixer.

24. The method of claim 23 wherein the mixer is switched by a carrier signal.