APPARATUS AND METHOD FOR MAPPING BINARY TO TERNARY AND ITS REVERSE

• US 20160087646A1
• Filed: 09/18/2014
• Published: 03/24/2016
• Est. Priority Date: 09/18/2014
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Motwani, Ravi H., Kalavade, Pranav
• Granted Patent: US 10,454,495 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03M 5/16 the pulses having three levels
• CPC Class Codes: H03M 7/02 Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word

Abstract

Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

Claims

1. An apparatus comprising:

a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and

a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

2. The apparatus of claim 1 comprises:

a second LUT having a mapping of 12 ternary trits to 19 binary bits; and

a second logic to receive the ternary output and to convert it to a binary output according to the second LUT.

3. The apparatus of claim 1, wherein the first LUT includes 19 entries corresponding to the power of 2 values in ternary for power of 2 from 0 to 18.

4. The apparatus of claim 2, wherein the second LUT includes 12 entries corresponding to the power of 3 values in binary for power of 3 from 0 to 11.

5. The apparatus of claim 1, wherein the first logic comprises:

logic to initialize the ternary output to zero.

6. The apparatus of claim 5, wherein the first logic comprises:

logic to determine the location of ones in binary input.

7. The apparatus of claim 6, wherein the binary input has 19 binary bits.

8. The apparatus of claim 6, wherein the first logic comprises logic to detect a one in the binary input.

9. The apparatus of claim 6, wherein the first logic comprises:

logic to read from the first LUT a ternary representation according to a corresponding location of one from the location of ones in the binary input.

10. The apparatus of claim 9, wherein the first logic comprises an adder to add, in ternary domain, the ternary representation to the initialized ternary output to generate the ternary output.

11. The apparatus of claim 10, wherein the ternary output is a 12 ternary symbol value.

12. The apparatus of claim 2, wherein the second logic comprises:

logic to read the ternary output and to initialize the binary output to zero.

13. The apparatus of claim 12, wherein the second logic comprises:

logic to determine location of ones in the 12 ternary trits of the ternary output;

logic to read from the second LUT a binary representation according to a corresponding location of one from the location of ones in the ternary input; and

an adder to add, in binary domain, the binary representation to the initialized binary output to generate the binary output.

14. A system comprising:

a non-volatile memory;

a processor coupled to the non-volatile memory, the processor including;

a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits;

a second LUT having a mapping of 12 ternary trits to 19 binary bits;

a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT; and

an encoder to receive the ternary output and encode the ternary output to generate an encoded ternary output for storing in the non-volatile memory; and

a wireless interface for allowing the processor to communicate with another device.

15. The system of claim 14 comprises:

a decoder to decode the encoded ternary output and to generate decoded ternary output.

16. The system of claim 15 comprises:

a second logic to receive the decoded ternary output and to convert it to a binary output according to the second LUT.

17. The system of claim 14, wherein the encoder is a ternary LDPC encoder, and wherein the decoder is a ternary LDPC decoder.

18. The system of claim 14, wherein the first LUT includes 19 entries corresponding to the power of 2 values in ternary for power of 2 from 0 to 18, and wherein the second LUT includes 12 entries corresponding to the power of 3 values in binary for power of 3 from 0 to 11.

19. A method comprising:

receiving a binary input; and

converting the binary input to a ternary output according to a first look-up table (LUT), the first LUT having a mapping of 19 binary bits to 12 ternary trits.

20. The method of claim 19 comprises:

receiving the ternary output; and

converting the ternary output to a binary output according to a second LUT, the second LUT having a mapping of 12 ternary trits to 19 binary bits.