CONTROL SYSTEMS FOR REDUCING CURRENT TRANSIENTS
First Claim
1. A controller used to reduce a frequency and/or a peak current value of a transient current induced by an input current supplied, by a power supply, to a computing system having at least one processor, the controller comprising:
- an input current filter operable at a first frequency and arranged to sample the input current; and
a control effort generator coupled to the input current filter, the control effort operable at a second frequency that is less than the first frequency and configured to use a sampled input current to provide a control effort signal to the at least one processor to reduce the frequency and/or the peak current value of the transient current by throttling the at least one processor thereby reducing a performance state of the at least one processor.
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Accused Products
Abstract
A method, apparatus, and system for reducing current transients of a power supply are disclosed. Specifically, the embodiments discussed herein include a control system configured to throttle a processor of a computing device when the current demanded by the processor from the power supply exceeds a reference current value. Throttling can include reducing or limiting the performance state that the processor can be operable in. Additionally, the control system can be operated according to multiple time domains, allowing the sampling of an input current to be performed at a higher rate than a rate at which analysis on the sampled input current is performed. The processor can remain throttled depending on a delayed release filter, which determines when a processor can return to a performance state that was previously removed.
14 Citations
20 Claims
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1. A controller used to reduce a frequency and/or a peak current value of a transient current induced by an input current supplied, by a power supply, to a computing system having at least one processor, the controller comprising:
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an input current filter operable at a first frequency and arranged to sample the input current; and a control effort generator coupled to the input current filter, the control effort operable at a second frequency that is less than the first frequency and configured to use a sampled input current to provide a control effort signal to the at least one processor to reduce the frequency and/or the peak current value of the transient current by throttling the at least one processor thereby reducing a performance state of the at least one processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A system for temporarily reducing a current demand of at least one processor, the system comprising:
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a sample generator configured to; sample an input current according to a first time domain, and output a current sample from a sample buffer of the sample generator according to a second time domain; and a process limiter operatively coupled to the sample generator and configured to provide a control effort signal according to a signal delay to limit an activity of the at least one processor and delay an increase in the activity of the at least one processor. - View Dependent Claims (13, 14, 15)
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16. A method for temporarily limiting a power consumption of a processor in response to an increased current demand of the processor from a power supply, the method comprising:
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receiving a sampled input current from a sample storage configured to; include an input and output contemporaneously operable at different frequencies, sample an input current, between the processor and power supply, and output the sampled input current for comparison to a reference value associated with the power supply; and limiting the power consumption of the processor when the sampled input current reaches at least the reference value. - View Dependent Claims (17, 18, 19, 20)
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Specification