HARDWARE APPARATUSES AND METHODS TO CONTROL CACHE LINE COHERENCY

• US 20160092354A1
• Filed: 09/26/2014
• Published: 03/31/2016
• Est. Priority Date: 09/26/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Steely, Simon C. Jr., Hasenplaugh, William C., Sury, Samantika S.
• Granted Patent: US 9,934,146 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

Methods and apparatuses to control cache line coherency are described. A processor may include a first core having a cache to store a cache line, a second core to send a request for the cache line from the first core, moving logic to cause a move of the cache line between the first core and a memory and to update a tag directory of the move, and cache line coherency logic to create a chain home in the tag directory from the request to cause the cache line to be sent from the tag directory to the second core. A method to control cache line coherency may include creating a chain home in a tag directory from a request for a cache line in a first processor core from a second processor core to cause the cache line to be sent from the tag directory to the second processor core.

Claims

1. A hardware apparatus comprising:

a first processor core having a cache to store a cache line;

a second processor core to send a request for the cache line from the first processor core;

moving logic to cause a move of the cache line between the first processor core and a memory and to update a tag directory of the move; and

cache line coherency logic to create a chain home in the tag directory from the request to cause the cache line to be sent from the tag directory to the second processor core.

2. The hardware apparatus of claim 1, wherein the move comprises a victim operation to remove the cache line from the first processor core.

3. The hardware apparatus of claim 2, wherein the victim operation is to remove the cache line from a victim buffer of the first processor core.

4. The hardware apparatus of claim 1, wherein the move comprises a back-invalidate operation.

5. The hardware apparatus of claim 4, wherein the chain home comprises an invalid acknowledgement field.

6. The hardware apparatus of claim 1, wherein the chain home comprises a requestor core field.

7. The hardware apparatus of claim 1, wherein the chain home comprises a live field to indicate that the move is in progress and the chain home is created in the tag directory.

8. The hardware apparatus of claim 1, wherein the chain home comprises a filled field to indicate that the second processor core sent the request for the cache line from the first processor core while the move is in progress.

9. A method to control cache line coherency comprising:

receiving a request for a cache line stored in a first processor core from a second processor core;

causing a move of the cache line between the first processor core and a memory and updating a tag directory of the move; and

creating a chain home in the tag directory from the request to cause the cache line to be sent from the tag directory to the second processor core.

10. The method of claim 9, wherein the causing the move comprises performing a victim operation to remove the cache line from the first processor core.

11. The method of claim 10, wherein the performing the victim operation removes the cache line from a victim buffer of the first processor core.

12. The method of claim 9, wherein the causing the move comprises performing a back-invalidate operation.

13. The method of claim 9, wherein the creating the chain home comprises updating a requestor core field.

14. The method of claim 9, wherein the creating the chain home comprises updating a live field to indicate that the move is in progress and the chain home is created in the tag directory.

15. The method of claim 9, wherein the creating the chain home comprises updating a filled field to indicate that the second processor core sent the request for the cache line from the first processor core while the move is in progress.

16. A hardware system comprising:

a system memory;

a first processor core having a cache to store a cache line;

a second processor core to send a request for the cache line from the first processor core;

moving logic to cause a move of the cache line between the first processor core and the system memory and to update a tag directory of the move; and

cache line coherency logic to create a chain home in the tag directory from the request to cause the cache line to be sent from the tag directory to the second processor core.

17. The hardware system of claim 16, wherein the move comprises a victim operation to remove the cache line from the first processor core.

18. The hardware system of claim 17, wherein the victim operation is to remove the cache line from a victim buffer of the first processor core.

19. The hardware system of claim 16, wherein the move comprises a back-invalidate operation.

20. The hardware system of claim 16, wherein the chain home comprises a requestor core field.

21. The hardware system of claim 16, wherein the chain home comprises a live field to indicate that the move is in progress and the chain home is created in the tag directory.

22. The hardware system of claim 16, wherein the chain home comprises a filled field to indicate that the second processor core sent the request for the cache line from the first processor core while the move is in progress.