MEMORY NETWORK TO ROUTE MEMORY TRAFFIC AND I/O TRAFFIC

• US 20160092362A1
• Filed: 04/30/2013
• Published: 03/31/2016
• Est. Priority Date: 04/30/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Barron, Dwight, Faraboschi, Paolo, Jouppi, Norman P., Krause, Michael R., Li, Sheng
• Granted Patent: US 9,952,975 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.

Claims

1. A memory network comprising:

memory nodes to provide shared memory for compute nodes and execute memory access commands for the compute nodes; and

links connecting the memory nodes and connecting the memory nodes and the compute nodes,

wherein memory traffic including the memory access commands is routable between the compute nodes and the memory nodes via the links in the memory network, and input/output (I/O) traffic is routable between the compute nodes and peripherals via the links in the memory network.

2. The memory network of claim 1, wherein the compute nodes cache data in local memory and are to store the cached data in the memory nodes, and the memory traffic includes messages between the compute nodes or between the compute nodes and the memory nodes to implement a cache coherency protocol or a non-coherent protocol.

3. The memory network of claim 2, wherein the cache coherency protocol comprises a snoop-based or a directory-based cache coherency protocol, and for the directory-based cache coherency protocol, the memory nodes include a directory controller to maintain a directory to indicate cache coherence among the compute nodes.

4. The memory network of claim 2, wherein the non-coherent protocol comprises a global address space protocol in the memory network.

5. The memory network of claim 2, wherein the non-coherent protocol comprises a message passing protocol in the memory network.

6. The memory network of claim 1, wherein the I/O traffic comprises network messages or other I/O messages between the compute nodes and the peripherals.

7. The memory network of claim 1, wherein the peripherals include at least one of a network interface controller, an I/O controller, a storage controller and a bridging device bridging memory networks.

8. The memory network of claim 1, wherein the memory traffic and the I/O traffic include packets routed by the memory nodes toward a final destination.

9. The memory network of claim 8, wherein the memory traffic or the I/O traffic includes a message including a pointer to a data block in a memory node, and a receiver of the message fetches the data block from the memory node using the pointer.

10. The memory network of claim 1, wherein a memory access and its associated coherence transaction are combined as one transaction for a cache coherency protocol implemented by the memory network.

11. A memory node in a memory network including memory nodes and compute nodes, wherein the memory nodes execute memory access commands for the compute nodes, the memory node comprising:

memory to store data blocks that are cached in the compute nodes; and

control logic to route the memory access commands in the memory network and execute a memory access command destined for the memory node and to route other traffic in the memory network toward its destination, wherein the other traffic includes input/output (I/O) traffic between the compute nodes and peripherals connected to the memory network.

13. The memory node of claim 11, wherein the memory traffic includes cache coherency protocols including at least one of a snoop-based and a directory-based cache coherency protocol.

14. The memory node of claim 11, wherein the memory network comprises a shared non-coherent memory system or a non-shared memory system.

12. The memory node of dam 11, wherein the peripherals include at least one of a network interface controller, an I/O controller, a storage controller and a bridging device bridging memory networks.

15. A method executed by a memory node including memory and control logic, wherein the memory node is in a memory network including memory nodes and compute nodes, and wherein the memory nodes operate as memory for the compute nodes, the method comprising:

storing data blocks for the compute nodes in the memory;

routing memory traffic in the memory network including memory access commands and control messages for at least one of a coherent memory system, a non-coherent shared memory system, and a non-shared memory systems and

routing other traffic in the memory network, wherein the other traffic includes input/output (I/O) traffic between the compute nodes and peripherals connected to the memory network.