MEMORY NETWORK TO ROUTE MEMORY TRAFFIC AND I/O TRAFFIC
First Claim
Patent Images
1. A memory network comprising:
- memory nodes to provide shared memory for compute nodes and execute memory access commands for the compute nodes; and
links connecting the memory nodes and connecting the memory nodes and the compute nodes,wherein memory traffic including the memory access commands is routable between the compute nodes and the memory nodes via the links in the memory network, and input/output (I/O) traffic is routable between the compute nodes and peripherals via the links in the memory network.
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Abstract
According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.
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Citations
15 Claims
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1. A memory network comprising:
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memory nodes to provide shared memory for compute nodes and execute memory access commands for the compute nodes; and links connecting the memory nodes and connecting the memory nodes and the compute nodes, wherein memory traffic including the memory access commands is routable between the compute nodes and the memory nodes via the links in the memory network, and input/output (I/O) traffic is routable between the compute nodes and peripherals via the links in the memory network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory node in a memory network including memory nodes and compute nodes, wherein the memory nodes execute memory access commands for the compute nodes, the memory node comprising:
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memory to store data blocks that are cached in the compute nodes; and control logic to route the memory access commands in the memory network and execute a memory access command destined for the memory node and to route other traffic in the memory network toward its destination, wherein the other traffic includes input/output (I/O) traffic between the compute nodes and peripherals connected to the memory network. - View Dependent Claims (13, 14)
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12. The memory node of dam 11, wherein the peripherals include at least one of a network interface controller, an I/O controller, a storage controller and a bridging device bridging memory networks.
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15. A method executed by a memory node including memory and control logic, wherein the memory node is in a memory network including memory nodes and compute nodes, and wherein the memory nodes operate as memory for the compute nodes, the method comprising:
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storing data blocks for the compute nodes in the memory; routing memory traffic in the memory network including memory access commands and control messages for at least one of a coherent memory system, a non-coherent shared memory system, and a non-shared memory systems and routing other traffic in the memory network, wherein the other traffic includes input/output (I/O) traffic between the compute nodes and peripherals connected to the memory network.
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Specification