INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM3 CRYPTOGRAPHIC HASHING FUNCTIONALITY

• US 20160092688A1
• Filed: 09/26/2014
• Published: 03/31/2016
• Est. Priority Date: 09/26/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wolrich, Gilbert M., Gopal, Vinodh, Gulley, Sean M., Yap, Kirk S., Feghali, Wajdi K.
• Granted Patent: US 9,658,854 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields

Abstract

Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.

Claims

1. A processor comprising:

a decode stage to decode a first instruction for a SIMD SM3 hash round slice, the first instruction specifying a round-slice portion of the hashing algorithm, an intermediate hash value input operand, a source data operand set, and a round constant operand set; and

one or more execution units, responsive to the decoded first instruction, to;

perform an SM3 hashing round-slice set of round iterations upon the source data operand set, applying the intermediate hash value input operand and the round constant operand set; and

store a result of the first instruction in a SIMD destination register.

2. The processor of claim 1, wherein the first instruction specifies said SIMD destination register also as the intermediate hash value input operand.

3. The processor of claim 1, wherein the first instruction specifies said round-slice portion of the hashing algorithm by a first field in an immediate operand.

4. The processor of claim 3, wherein the first instruction specifies said round constant operand set at least in part by a second field in the immediate operand.

5. The processor of claim 4, wherein the first instruction further specifies a Boolean function FF_j and GG_j selector by said second field in the immediate operand.

6. The processor of claim 1, wherein the first instruction specifies said round-slice portion of the hashing algorithm in a first instruction mnemonic to be four rounds.

7. The processor of claim 6, wherein said round constant operand set comprises four pre-rotated 32-bit constant values.

8. The processor of claim 1, wherein the first instruction specifies said round-slice portion of the hashing algorithm in a first instruction mnemonic to be two rounds.

9. The processor of claim 1, wherein the first instruction specifies said round-slice portion of the hashing algorithm in a first instruction mnemonic to be one round.

10. The processor of claim 1, wherein the first instruction specifies said source data operand set as a SIMD register comprising eight 32-bit values.

11. The processor of claim 1, wherein the first instruction specifies said source data operand set as a memory location comprising eight 32-bit values.

12. The processor of claim 1, wherein the first instruction specifies said source data operand set as two SIMD registers each comprising four 32-bit values.

13. The processor of claim 1, wherein the first instruction specifies said round-slice portion of the hashing algorithm by a first field in an immediate operand to store a round number between 0 and 63 and by a second field to store an iteration count between 0 and 3.

14. A processor comprising:

a decode stage to decode a first instruction for a SIMD SM3 message expansion, the first instruction specifying a first source data operand set, a second source data operand set, and an expansion extent; and

one or more execution units, responsive to the decoded first instruction, to;

perform a number of SM3 message expansions from the first and second source data operand sets, the number of SM3 message expansions being determined by the specified expansion extent; and

store a result of the first instruction in a SIMD destination register.

15. The processor of claim 14, wherein the first instruction specifies said SIMD destination register as a destination operand.

16. The processor of claim 14, wherein the first instruction specifies said first and second source data operand sets as two SIMD registers each comprising eight 32-bit values.

17. The processor of claim 14, wherein the first instruction specifies said expansion extent by a first field in an immediate operand.

18. The processor of claim 14, wherein the first instruction specifies said expansion extent in a first instruction mnemonic to indicate a message expansion of four new 32-bit words.

19. The processor of claim 18, wherein the message expansion for one of the four new 32-bit words requires one other of the four new 32-bit words in addition to the first and second source data operand sets.

20. The processor of claim 14, wherein the first instruction specifies said expansion extent in a first instruction mnemonic to indicate a message expansion of two new 32-bit words.

21. The processor of claim 14, wherein the first instruction specifies said expansion extent in a first instruction mnemonic to indicate a message expansion of one new 32-bit word.

22. The processor of claim 14, wherein the first instruction specifies said expansion extent in a first instruction mnemonic to indicate a message expansion of four new 32-bit words.

23. A method comprising:

storing in a first portion of a plurality of m data fields of a first vector register, an intermediate hash value input state source operand of an SM3 hash algorithm;

storing in a second portion of the plurality of m data fields of a second vector register, a source data operand set;

executing, in a processor, a SIMD instruction for an SM3 hash-round-slice portion of the SM3 hashing algorithm having a plurality of iterations less that a total number of round iterations of the SM3 hash algorithm; and

for each iteration of the SM3 hash-round-slice, generating a result of an iteration, storing a hash value output state generated as the result of the iteration, and bypassing the hash value output state to the intermediate hash value input state for each next iteration of the plurality of iterations.

24. The method of claim 23 further comprising:

storing in a third portion of the plurality of m data fields of a third vector register, a round constant operand set; and

for each iteration of the SM3 hash-round-slice, reading a respective round constant, T_j, of the round constant operand set and adding the respective round constant with a left-rotated respective data field, A, of the first vector register and a second unrotated data field, E, of the first vector register.

25. The method of claim 24 wherein said third portion comprises four of the plurality of m data fields of the third vector register, and each round constant, T_j, of the stored round constant operand set is pre-rotated left by j bits.

26. The method of claim 23 further comprising:

for each iteration of the SM3 hash-round-slice, reading a respective data field, W_j, of the second vector register and XORing the respective data field of the second vector register with a second data field, W_j+4, of the second vector register.

27. The method of claim 26 wherein said second portion comprises eight of the plurality of m data fields of the second vector register.

28. The method of claim 23 wherein said first portion comprises eight of the plurality of m data fields of the first vector register.

29. The method of claim 23 wherein the SIMD instruction specifies said round-slice portion of the SM3 hashing algorithm by a first field in an immediate operand.

30. The method of claim 29 wherein the SIMD instruction specifies a round constant operand set at least in part by a second field in the immediate operand.

31. The method of claim 30 wherein the SIMD instruction further specifies a Boolean function FF_j and GG_j selector by said second field in the immediate operand.

32. A method comprising:

storing in a first portion of a plurality of m data fields of a first vector register, a first source data operand set;

storing in a second portion of the plurality of m data fields of a second vector register, a second source data operand set;

executing, in a processor, a SIMD instruction specifying an expansion extent for an SM3 message-expansion-slice portion for the SM3 hashing algorithm having a number of SM3 message expansions from the first and second source data operand sets, the number of SM3 message expansions being determined by the specified expansion extent; and

storing a result of the SIMD instruction in a SIMD destination register.

33. The method of claim 32, wherein the SIMD instruction specifies said first and second source data operand sets as two SIMD registers each comprising eight 32-bit values.

34. The method of claim 32, wherein the SIMD instruction specifies said expansion extent by a first field in an immediate operand.

35. The method of claim 32, wherein the SIMD instruction specifies said expansion extent in a first instruction mnemonic to indicate a message expansion of four new 32-bit words.

36. The method of claim 35, wherein the message expansion for one of the four new 32-bit words requires one other of the four new 32-bit words in addition to the first and second source data operand sets.

37. A processing system comprising:

a memory to store a first instruction for a SIMD SM3 hashing algorithm round slice, and a second instruction for an SM3 message expansion slice for the SM3 hashing algorithm; and

a processor comprising;

an instruction fetch stage to fetch the first instruction;

a decode stage to decode the first instruction, the first instruction specifying specifying a round-slice portion of the hashing algorithm, an intermediate hash value input operand, a round-slice source data operand set, and a round constant operand set;

the decode stage to decode the second instruction, the second instruction specifying a first source data operand set, a second source data operand set, and an expansion extent; and

one or more execution units, responsive to the decoded first instruction, to;

perform an SM3 hashing round-slice set of round iterations upon the round-slice source data operand set, applying the intermediate hash value input operand and the round constant operand set, and storing a first result of the first instruction in a first SIMD destination register; and

the one or more execution units, responsive to the decoded second instruction, to;

perform a number of SM3 message expansions from the first and second source data operand sets, the number of SM3 message expansions being determined by the specified expansion extent, and storing a second result of the second instruction in a second SIMD destination register.

38. The processing system of claim 37, wherein the first instruction specifies said round-slice portion of the hashing algorithm by a first field in an immediate operand.

39. The processing system of claim 37, wherein the first instruction specifies said round constant operand set at least in part by a second field in the immediate operand.

40. The processing system of claim 39, wherein the first instruction further specifies a Boolean function FF_j and GG_j selector by said second field in the immediate operand.

41. The processing system of claim 37, wherein the first instruction specifies said round-slice portion of the hashing algorithm in a first instruction mnemonic to be four rounds.

42. The processing system of claim 41, wherein said round constant operand set comprises an initial pre-rotated 32-bit constant value.

43. The processing system of claim 42, wherein said round constant operand set comprises four pre-rotated 32-bit constant values.

44. The processing system of claim 37, wherein the second instruction specifies said first and second source data operand sets as two SIMD registers each comprising eight 32-bit values.

45. The processing system of claim 37, wherein the second instruction specifies said expansion extent by a first field in an immediate operand.

46. The processing system of claim 37, wherein the second instruction specifies said expansion extent in a first instruction mnemonic to indicate a message expansion of four new 32-bit words.