NONVOLATILE MEMORY MODULE

• US 20160093377A1
• Filed: 09/26/2014
• Published: 03/31/2016
• Est. Priority Date: 09/26/2014
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Prakash, Mani, Payton, Edward L., Ziakas, Dimitrios, Ramanujan, Raj K., Wang, Dong, Grooms, John K., Arafa, Mohammed
• Application Number:
  US14/498,480
• Publication Number:
  US 20160093377A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed.

Claims

1. A memory module comprising:

a nonvolatile memory;

an interface to a volatile memory bus;

at least one input power rail to receive power from a host platform; and

a controller comprising logic, at least partially including hardware logic, to;

convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage.

2. The memory module of claim 1, wherein the volatile memory bus comprises at least one of:

a double data rate synchronous dynamic random access memory (DDRx-SDRAM) bus;

a DDR SDRAM bus, or

a DDR4 SDRAM bus.

3. The memory module of claim 1, wherein the controller comprises logic, at least partially including hardware logic, to:

generate a varied output voltage comprising at least a first output voltage on a first output rail to a second output voltage on a second output rail.

4. The memory module of claim 1, wherein the controller comprises logic, at least partially including hardware logic, to:

vary the output voltage on at least one of the first output rail or the second output rail.

5. The memory module of claim 1, wherein the controller comprises logic, at least partially including hardware logic, to:

initiate a power up sequence on the memory module when the power received from the host platform at the input power rail reaches a threshold voltage.

6. The memory module of claim 4, wherein the power up sequence implements a first delay before providing power to the first output rail and a second delay before providing power to the second output rail.

7. The memory module of claim 1, further comprising an energy storage device coupled to the memory module.

8. The memory module of claim 6, wherein the controller comprises logic to detect a power fail condition, and in response to the power fail condition to implement a power fail sequence.

9. The memory module of claim 7, wherein the power fail sequence draws power from at least one energy store coupled to the memory module to provide power to enable an orderly power down of one or more components on the memory module.

10. The memory module of claim 6, wherein the controller comprises logic to detect a power reset signal, and in response to the power reset signal to implement a power reset sequence.

11. The memory module of claim 9, wherein the power reset sequence draws power from at least one energy store coupled to the memory module to provide power to enable an orderly power down of one or more components on the memory module.

14. The electronic device of claim 11, wherein the controller comprises logic, at least partially including hardware logic, to:

generate a varied output voltage comprising at least a first output voltage on a first output rail to a second output voltage on a second output rail.

15. The electronic device of claim 11, wherein the controller comprises logic, at least partially including hardware logic, to:

vary the output voltage on at least one of the first output rail or the second output rail.

16. The electronic device of claim 11, wherein the controller comprises logic, at least partially including hardware logic, to:

initiate a power up sequence on the memory module when the power received from the host platform at the input power rail reaches a threshold voltage.

17. The electronic device of claim 14, wherein the power up sequence implements a first delay before providing power to the first output rail and a second delay before providing power to the second output rail.

18. The electronic device of claim 11, further comprising an energy storage device coupled to the memory module.

19. The electronic device of claim 16, wherein the controller comprises logic to detect a power fail condition, and in response to the power fail condition to implement a power fail sequence.

20. The electronic device of claim 17, wherein the power fail sequence draws power from at least one energy store coupled to the memory module to provide power to enable an orderly power down of one or more components on the memory module.

21. The electronic device of claim 16, wherein the controller comprises logic to detect a power reset signal, and in response to the power reset signal to implement a power reset sequence.

22. The electronic device of claim 19, wherein the power reset sequence draws power from at least one energy store coupled to the memory module to provide power to enable an orderly power down of one or more components on the memory module.

12. An electronic device, comprising:

a processor to execute an operating system and at least one application;

a memory module comprising;

a nonvolatile memory;

an interface to a volatile memory bus;

at least one input power rail to receive power from a host platform; and

a controller comprising logic, at least partially including hardware logic, to;

convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage.

13. The electronic device of claim 12, wherein the volatile memory bus comprises at least one of:

a double data rate synchronous dynamic random access memory (DDRx-SDRAM) bus;

a DDR SDRAM bus, or

a DDR4 SDRAM bus.