MEMORY DEVICE INCLUDING NONVOLATILE MEMORY CELL
First Claim
1. A memory device including nonvolatile memory cells, each of which comprises:
- an active pattern including first to fourth regions successively arranged in one direction;
a first gate structure crossing the active pattern on the second region and including a first gate electrode and a first insulating layer; and
a second gate structure crossing the active pattern on the fourth region and including a second gate electrode and a second insulating layer,wherein the nonvolatile memory cell is configured such that;
a first voltage is applied to the second gate electrode when the second insulating layer is in a first state such that a current that passes through the second region becomes a first current,the first voltage is applied to the second gate electrode when the second insulating layer is in a second state such that a current that passes through the second region becomes a second current,the first voltage is applied to the second gate electrode when the second insulating layer is in a third state such that a current that passes through the second region becomes a third current,the second current and the third current are higher than the first current, andthe second current is different from the third current.
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Accused Products
Abstract
A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.
8 Citations
20 Claims
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1. A memory device including nonvolatile memory cells, each of which comprises:
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an active pattern including first to fourth regions successively arranged in one direction; a first gate structure crossing the active pattern on the second region and including a first gate electrode and a first insulating layer; and a second gate structure crossing the active pattern on the fourth region and including a second gate electrode and a second insulating layer, wherein the nonvolatile memory cell is configured such that; a first voltage is applied to the second gate electrode when the second insulating layer is in a first state such that a current that passes through the second region becomes a first current, the first voltage is applied to the second gate electrode when the second insulating layer is in a second state such that a current that passes through the second region becomes a second current, the first voltage is applied to the second gate electrode when the second insulating layer is in a third state such that a current that passes through the second region becomes a third current, the second current and the third current are higher than the first current, and the second current is different from the third current. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory device including nonvolatile memory cells, each of which comprises:
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an active pattern including first to fourth regions successively arranged in one direction; a first gate structure crossing the active pattern on the second region and including a first gate electrode and a first insulating layer; and a second gate structure crossing the active pattern on the fourth region and including a second gate electrode and a second insulating layer, wherein the first region is connected to a sense amplifier that detects a current passing through the second region, wherein if the nonvolatile memory cell is a One-Time Programmable (OTP) cell before the second insulating layer is programmed or is a Multi-Time Programmable (MTP) cell before the second insulating layer is formed, the second insulating layer has a first resistance value, wherein if the nonvolatile memory cell is the OTP cell, the second insulating layer has a second resistance value that is smaller than the first resistance value in the nonvolatile memory cell that is in a programmed state, and wherein if the nonvolatile memory cell is the MTP cell, the second insulating layer has a third resistance value that is smaller than the first resistance value and is larger than the second resistance value in the nonvolatile memory cell that is in a set state. - View Dependent Claims (12, 13)
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14. A memory device comprising:
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a row decoder configured to select a word line of a plurality of word lines; a column decoder configured to select a bit line of a plurality of bit lines; a first set of memory cells connected to corresponding word lines of the plurality of word lines and corresponding bit lines of the plurality of bit lines, each memory cell of the first set of memory cells having a first state and a second state opposite to the first state; and a second set of memory cells connected to corresponding word lines of the plurality of word lines and corresponding bit lines of the plurality of bit lines, each memory cell of the second set of memory cells having a third state and a fourth state opposite to the third state, wherein a first memory cell of the first set of memory cells having a first resistance value has the first state and a second memory cell of the first set of memory cells having a second resistance value less than the first resistance value has the second state, and wherein a first memory cell of the second set of memory cells having a third resistance value less than the first resistance value and greater than the second resistance value has the third state, and a second memory cell of the second set of memory cells having a fourth resistance value less than the third resistance value and greater than the second resistance value has the fourth state. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification