ALL VOLTAGE, TEMPERATURE AND PROCESS MONITOR CIRCUIT FOR MEMORIES

• US 20160093399A1
• Filed: 11/06/2014
• Published: 03/31/2016
• Est. Priority Date: 09/25/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: GUPTA, Saket, ZHANG, Yifei, MONZEL, Carl, WINTER, Mark Jon
• Granted Patent: US 9,324,451 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A device for monitoring process variations across memory bitcells includes a bitcell inverter that provides an output voltage to be used for identifying skewed corners of the memory bitcells. A first comparator compares the output voltage with a first reference voltage, and a second comparator compares the output voltage with a second reference voltage. The first and the second comparators generate a corner code based on comparison results.

Claims

1. A device for monitoring process variations across memory bitcells, the device comprising:

a bitcell inverter configured to provide an output voltage to be used for identifying skewed corners of the memory bitcells;

a first comparator configured to compare the output voltage with a first reference voltage; and

a second comparator configured to compare the output voltage with a second reference voltage,

wherein the first and the second comparators are configured to generate a corner code based on comparison results, and wherein the first reference voltage is greater than the second reference voltage.

2. The device of claim 1, wherein the bitcell inverter comprises a first portion of a memory bitcell and a second portion of the memory bitcell.

3. The device of claim 2, wherein the memory bitcells comprise CMOS memory bitcells, and wherein the first portion comprises a PMOS transistor and the second portion comprises an NMOS transistor.

4. The device of claim 3, wherein the bitcell inverter is configured by coupling a gate node of the PMOS transistor to a gate node of the NMOS transistor.

5. The device of claim 3, wherein the PMOS transistor comprises a pull-up PMOS transistor of the CMOS memory bitcell and the NMOS transistor comprises a pass-gate NMOS transistor of the CMOS memory bitcell.

6. The device of claim 1, wherein the bitcell inverter is biased at a trip-point of a CMOS memory bitcell.

7. The device of claim 1, wherein the first and the second comparators are configured to generate a code corresponding to a SF corner when the output voltage is greater than the first reference voltage.

8. The device of claim 1, wherein the first and the second comparators are configured to generate a code corresponding to a FS corner when the output voltage is smaller than the second reference voltage.

9. The device of claim 1, wherein the corner code is provided to an adaptive assist circuit that provides an adaptive assist setting output to a memory assist circuit, and wherein the device is configured to enable the adaptive assist circuit in a low-voltage mode (LVM) operation.

10. A method for monitoring process variations across memory bitcells, the method comprising:

configuring a bitcell inverter to provide an output voltage in response to an enable signal;

providing a first comparator that is configured to compare the output voltage with a first reference voltage;

providing a second comparator that is configured to compare the output voltage with a second reference voltage; and

configuring the first and the second comparators to generate a corner code based on comparison results,

wherein the corner code is configured to be used for identifying skewed corners of the memory bitcells, and wherein the first reference voltage is greater than the second reference voltage.

11. The method of claim 10, wherein the bitcell inverter comprises a first portion of a memory bitcell and a second portion of the memory bitcell of a memory chip.

12. The method of claim 11, wherein the memory bitcells comprise CMOS memory bitcells, and wherein the first portion comprises a PMOS transistor and the second portion comprises an NMOS transistor.

13. The method of claim 12, wherein configuring the bitcell inverter comprises coupling a gate node of the PMOS transistor to a gate node of the NMOS transistor.

14. The method of claim 12, wherein coupling the gate node of the PMOS transistor to the gate of the NMOS transistor comprises coupling a pull-up PMOS transistor of the CMOS memory bitcell to the gate node of the NMOS transistor, and wherein the NMOS transistor comprises a pass-gate NMOS transistor of the CMOS memory bitcell.

15. The method of claim 10, wherein configuring biasing the bitcell inverter comprises biasing the bitcell inverter at a trip-point of a CMOS memory bitcell.

16. The method of claim 10, and wherein the method further comprising configuring the first and the second comparators to generate a code corresponding to a SF corner when the output voltage is greater than the first reference voltage.

17. The method of claim 10, further comprising configuring the first and the second comparators to generate a code corresponding to a FS corner when the output voltage is smaller than the second reference voltage.

18. The method of claim 10, further comprising providing the corner code to an adaptive assist circuit that provides an adaptive assist setting output to a memory assist circuit, and enable enabling the adaptive assist circuit in a low-voltage mode (LVM) operation.

19. A communication device, comprising:

memory comprising memory bitcells; and

a device for monitoring process variations across the memory bitcells, the device comprising;

a bitcell inverter configured to provide an output voltage in response to an enable signal;

a first comparator configured to compare the output voltage with a first reference voltage; and

a second comparator configured to compare the output voltage with a second reference voltage,

wherein the first and the second comparators are configured to generate a corner code based on comparison results, and wherein the corner code is configured to be used for identifying skewed corners of the memory bitcells, and wherein the first reference voltage is greater than the second reference voltage.

20. The communication device of claim 19, wherein:

the memory bitcells comprise CMOS memory bitcells,

the bitcell inverter comprises a first portion of a memory bitcell and a second portion of the memory bitcell,

the first portion comprises a PMOS transistor and the second portion comprises an NMOS transistor,

the bitcell inverter is configured by coupling a gate node of the PMOS transistor to a gate of the NMOS transistor,

the PMOS transistor comprises a pull-up PMOS transistor of the CMOS memory bitcell and the NMOS transistor comprises a pass-gate NMOS transistor of the CMOS memory bitcell, and

the bitcell inverter is biased at a trip-point of a CMOS memory bitcell.