APPARATUS AND METHOD OF MANUFACTURING FIN-FET DEVICES

• US 20160093537A1
• Filed: 09/30/2014
• Published: 03/31/2016
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, Chang-Yin, CHENG, Tung-Wen, CHANG, Che-Cheng, LIN, Jr-Jung, LIN, Chih-Han
• Granted Patent: US 9,620,417 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/32449 Gas control, e.g. control of the gas flow
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.

Claims

1. A method of manufacturing a Fin-FET device, comprising:

forming a plurality of fins in a substrate, wherein the substrate comprises a center region and a periphery region surrounding the center region;

depositing a gate material layer over the fins; and

etching the gate material layer with an etching gas to form gates, wherein the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.

2. The method of claim 1, wherein the gate formed at the center region and the gate formed at the periphery region both have a notched feature.

3. The method of claim 1, wherein the gate has a first portion disposed above the fin and a second portion overlapped with the sidewalls of the fin.

4. The method of claim 3, wherein the second portion comprises:

a first width at a boundary of the first portion and the second portion; and

a second width at a bottom of the gate, wherein the second width is smaller than the first width.

5. The method of claim 4, further comprising a third width between the first width and the second width, wherein the third with is smaller than the second width.

6. The method of claim 1, wherein the etching gas is hydrogen bromide or oxygen.

7. The method of claim 1, further comprising growing an epitaxial structure in the fin.

8. The method of claim 7, wherein the epitaxial structure is formed of SiGe.

9. The method of claim 7, wherein a proximity distance between the epitaxial structure and the gate is in a range from about 0.5 nm to about 10 nm.

21. The method of claim 1, wherein the etching gas is supplied at the ratio of the flow rate at the center region to the flow rate at the periphery region in a range from 1 to 1.1.

22. The method of claim 1, wherein depositing the gate material layer over the fins comprises:

forming a gate oxide layer over the fins;

forming a gate layer on the gate oxide layer; and

forming a hard mask layer on the gate layer.

10. A method of manufacturing a Fin-FET device, comprising:

forming a plurality of fins in a substrate, wherein the substrate comprises a center region and a periphery region surrounding the center region;

depositing a gate material layer over the fins;

etching the gate material layer with an etching gas; and

forming gates from the etched gate material layer in a predetermined shape by supplying the etching gas at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3, wherein the predetermined shape has a first portion disposed above the fin and a second portion overlapped with the sidewalls of the fin, wherein the second portion comprises;

a first width at a boundary of the first portion and the second portion;

a second width at a bottom of the gate;

a third width between the first width and the second width, wherein the third width is smaller than the first width and the second width; and

a first distance from the second width to the third width that is determined by the ratio.

11. The method of claim 10, wherein the etching gas is hydrogen bromide or oxygen.

12. The method of claim 10, wherein the second width is smaller than the first width.

13. The method of claim 10, further comprising growing an epitaxial structure in the fin.

14. The method of claim 13, wherein a proximity distance between the epitaxial structure and the gate is in a range from about 0.5 nm to about 10 nm.

23. The method of claim 10, wherein the he etching gas is supplied at the ratio of the flow rate at the center region to the flow rate at the periphery region in a range from 1 to 1.1.

24. The method of claim 13, wherein the third width is substantially aligned with an angle of the epitaxial structure.

25. The method of claim 10, wherein the first distance from the second width to the third width of the gate in the center region is increased by decreasing the ratio.

26. The method of claim 24, wherein the first distance from the second width to the third width of the gate in the periphery region is deceased by decreasing the ratio.

15-20. -20. (canceled)