MULTIHEIGHT ELECTRICALLY CONDUCTIVE VIA CONTACTS FOR A MULTILEVEL INTERCONNECT STRUCTURE

• US 20160093626A1
• Filed: 09/30/2014
• Published: 03/31/2016
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Izumi, Keisuke, Sano, Michiaki, Sasaki, Hiroshi
• Granted Patent: US 9,412,753 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of a plurality of alternating sacrificial layers and insulator layers located over a major surface of a substrate. A contact mask with at least one contact mask opening and at least one first terrace mask opening is provided over the stack, where the at least one first terrace mask opening is larger than the at least one contact mask opening. At least one first contact opening and at least one first terrace opening are simultaneously formed extending substantially perpendicular to the major surface of the substrate through the stack to a first sacrificial layer by etching a portion of the stack through the at least one contact mask opening and the at least one first terrace mask opening. A first electrically conductive via contact is deposited in the at least one first contact opening.

Claims

1. A method of making multi-level contacts, comprising:

providing an in-process multilevel device comprising a device region and a contact region comprising a stack of plurality of alternating sacrificial layers and insulating layers located over a major surface of a substrate;

providing a first contact mask with at least one first contact mask opening and at least one first terrace mask opening over the stack, wherein the at least one first terrace mask opening is larger than the at least one first contact mask opening;

simultaneously forming at least one first contact opening and at least one first terrace opening extending substantially perpendicular to the major surface of the substrate through the stack to a first sacrificial layer by etching a portion of the stack through the at least one first contact mask opening and the at least one first terrace mask opening; and

depositing a first electrically conductive via contact in the at least one first contact opening.

2. The method of claim 1, further comprising detecting an end point of the etching when the at least one terrace opening reaches the first sacrificial layer, and stopping the etching of the stack to form both the at least one first contact opening and at least one first terrace opening when the end point of the etching is detected.

3. The method of claim 1, further comprising:

removing the first contact mask;

providing a second contact mask with at least one second contact mask opening and at least one second terrace mask opening over the stack, wherein the at least one second terrace mask opening is larger than the at least one second contact mask opening;

simultaneously forming at least one second contact opening and at least one second terrace opening extending substantially perpendicular to the major surface of the substrate through the stack to a second sacrificial layer by etching a portion of the stack through the at least one second contact mask opening and the at least one second terrace mask opening; and

depositing a second electrically conductive via contact in the at least one second contact opening.

4. The method of claim 3, further comprising:

removing the second contact mask;

providing a third contact mask with at least one third contact mask opening and at least one third terrace mask opening over the stack, wherein the at least one third terrace mask opening is larger than the at least one third contact mask opening;

simultaneously forming at least one third contact opening and at least one third terrace opening extending substantially perpendicular to the major surface of the substrate through the stack to a third sacrificial layer by etching a portion of the stack through the at least one third contact mask opening and the at least one third terrace mask opening; and

depositing a third electrically conductive via contact in the at least one third contact opening.

5. The method of claim 4, further comprising:

simultaneously forming an insulating liner on a sidewall of the at least one first contact opening, the at least one second contact opening, and the at least one third contact opening, prior to depositing the first electrically conductive via contact;

simultaneously forming an insulating layer in the at least one first terrace opening, the at least one second terrace opening, and the at least one third terrace opening;

forming at least one first terrace contact opening, at least one second terrace contact opening, and at least one third terrace contact opening in the insulating layer;

depositing a first electrically conductive terrace via contact in the at least one first terrace contact opening;

depositing a second electrically conductive terrace via contact in the at least one second terrace contact opening; and

depositing a third electrically conductive terrace via contact in the at least one third terrace contact opening.

6. The method of claim 5, wherein forming the insulating liner comprises:

depositing an insulating material on the sidewall and bottom surface of the at least one first contact opening, the at least one second contact opening, and the at least one third contact opening; and

removing the insulating material from the bottom surface of the at least one first contact opening, the at least one second contact opening, and the at least one third contact opening.

7. The method of claim 3, wherein:

the first contact mask, the second contact mask and the third contact mask comprise a respective first, second and third photoresist layers;

the second sacrificial layer extends in a direction parallel to the major surface of the substrate past the first sacrificial layer in the at least one third terrace opening;

the third sacrificial layer extends in a direction parallel to the major surface of the substrate past the second sacrificial layer in the at least one third terrace opening;

the first, second and third sacrificial layers form a stepped pattern in the at least one third terrace opening;

the first sacrificial layer is located in a first device level and the second sacrificial layer is located in a second device level lower than the first device level; and

the first sacrificial layer extends around the at least one second contact opening.

8. The method of claim 5, wherein depositing the first electrically conductive terrace via contact, depositing the second electrically conductive terrace via contact, and depositing the third electrically conductive terrace via contact comprise a same deposition step.

9. The method of claim 5, further comprising:

forming a trench through the stack; and

selectively removing the sacrificial layers from the stack through at least one of the at least one first contact opening, the at least one second contact opening, the at least one third contact opening, and the trench to form a plurality of recesses;

wherein the plurality of recesses comprise a first recess in the first device level and a second recess in the second device level.

10. The method of claim 9, further comprising:

forming a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the major surface of the substrate in the device region;

forming a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

forming a plurality of electrically conductive electrodes in the plurality of recesses through the trench;

wherein;

a first electrically conductive electrode of the plurality of electrically conductive electrodes comprises a first control gate electrode which is formed in the first recess and extends around the second contact opening;

a second electrically conductive electrode of the plurality of electrically conductive electrodes comprises a second control gate electrode which is formed in the second recess;

the insulating liner on the sidewall of the first contact opening electrically isolates the second control gate electrode deposited in the second recess from the first electrically conductive via contact; and

the device comprises a vertical NAND device.

11. The method of claim 10, further comprising removing an electrically conductive electrode material of the plurality of electrically conductive electrodes from the trench, forming a trench insulating layer on a sidewall of the trench, and forming a source line in the trench such that the source line electrically contacts a portion of the device region of the device.

12. A three-dimensional NAND device, comprising:

a substrate having a major surface;

a stack of plurality of alternating word lines and insulating layers located over the major surface of the substrate and extending substantially parallel to the major surface of the substrate, wherein the plurality of word lines comprise at least a first word line located in a first device level and a second word line located in a second device level located over the major surface of the substrate and below the first device level;

a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to the major surface of the substrate through the stack;

at least one charge storage region located adjacent to the semiconductor channel;

a first plurality of electrically conductive via contacts extending substantially perpendicular to the major surface of the substrate, wherein each of the first plurality of electrically conductive via contacts extends through the stack to contact an upper surface of a respective one of the plurality of word lines in a first set of word lines;

an insulating liner located around each of the first plurality of electrically conductive via contacts, wherein the insulating liner isolates each of the first plurality of electrically conductive via contacts from all the word lines in the stack through which each electrically conductive via contact extends, except a respective one of the plurality of word lines whose upper surface is contacted by the respective electrically conductive via contact;

a terraced region in the stack comprising end portions of a second set of word lines arranged in a stepped configuration in which underlying word lines extend past overlying word lines in a direction parallel to the major surface of the substrate;

an insulating layer located above the terraced region in the stack; and

a second plurality of electrically conductive via contacts extending substantially perpendicular to the major surface of the substrate, wherein each of the second plurality of electrically conductive via contacts extends through the insulating layer to contact an upper surface of a respective one of the second set of word lines.

13. The device of claim 12, wherein:

the first set of word lines lacks the stepped configuration such that end portions of the first set of word lines terminate in a same vertical plane adjacent to the terraced region; and

the first set of word lines is located above the second set of word lines.

14. The device of claim 12, wherein:

the substrate comprises a silicon substrate;

the three-dimensional NAND device comprises a monolithic, three-dimensional array of NAND strings located over the silicon substrate;

at least one memory cell in a first device level of the three-dimensional array of NAND strings is located over another memory cell in a second device level of the three-dimensional array of NAND strings; and

the silicon substrate contains an integrated circuit comprising a driver circuit for the at least one memory cell.