NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM)

• US 20160093671A1
• Filed: 09/30/2014
• Published: 03/31/2016
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: ROY, ANIRBAN
• Granted Patent: US 10,446,608 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors

Abstract

A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.

Claims

1. A method of making a semiconductor device, the method comprising:

forming a first transistor structure over a substrate;

forming a second transistor structure over the substrate;

forming a capacitor structure as a trench in the substrate between the first and second transistor structures, the capacitor structure comprising;

a doped layer over the substrate;

a dielectric layer over the doped layer; and

a conductive fill material over the dielectric layer;

forming a first conductive contact from the first transistor structure to a first bit line;

forming a second conductive contact from the second transistor to a non-volatile memory element; and

forming a third conductive contact from the non-volatile memory element to a second bit line.

2. The method of claim 1, wherein the doped layer is electrically coupled to a source/drain portion of the first transistor structure.

3. The method of claim 1, wherein the doped layer is electrically coupled to a source/drain portion of the second transistor structure.

4. The method of claim 1, wherein the capacitor structure further comprises a conductive cap structure over the conductive fill material.

5. The method of claim 1, wherein the first conductive contact comprises:

a first via electrically coupled to a source/drain region of the first transistor structure;

a second via electrically coupled to the first bit line; and

a first portion of a first metal layer electrically coupled to the first and second vias.

6. The method of claim 5, wherein the second conductive contact comprises:

a first via electrically coupled to a source/drain region of the second transistor structure;

a second via;

a second portion of the first metal layer electrically coupled to the first and second vias;

a third via; and

a portion of a second metal layer electrically coupled to the second and third vias.

7. The method of claim 1, wherein the non-volatile memory element comprises a variable resistive element.

8. The method of claim 7, wherein the variable resistive element comprises one of a group consisting of:

a resistive random access memory element, a magnetic random access memory element, a phase-change memory resistive element, and a carbon nanotube resistive element.

9. A method of making a semiconductor device, the method comprising:

forming a first transistor structure over a substrate;

forming a second transistor structure over the substrate;

forming a capacitor structure in the substrate between the first and second transistor structures;

forming a first conductive contact from the first transistor structure to a first bit line;

forming a second conductive contact from the second transistor structure to a variable resistive element; and

forming a third conductive contact from the variable resistive element to a second bit line.

10. The method of claim 9, wherein the capacitor structure comprises a trench in the substrate, the capacitor structure comprising:

a doped layer over the substrate, the doped layer electrically coupled to a source/drain portion of the first transistor structure and to a source/drain portion of the second transistor structure;

a dielectric layer over the doped layer; and

a conductive fill material over the dielectric layer.

11. The method of claim 10, wherein the capacitor structure further comprises a conductive cap structure over the conductive fill material.

12. The method of claim 9, wherein the first conductive contact comprises:

a first via electrically coupled to a source/drain region of the first transistor structure;

a second via electrically coupled to the first bit line; and

a first portion of a first metal layer electrically coupled to the first and second vias.

13. The method of claim 12, wherein the second conductive contact comprises:

a first via electrically coupled to a source/drain region of the second transistor structure;

a second via;

a second portion of the first metal layer electrically coupled to the first and second vias;

a third via; and

a portion of a second metal layer electrically coupled to the second and third vias.

14. The method of claim 9, wherein the variable resistive element comprises one of a group consisting of:

an resistive random access memory element, a magnetic random access memory element, a phase-change memory resistive element, and a carbon nanotube resistive element.

15. A semiconductor device comprising:

a first transistor structure over a substrate;

a second transistor structure over the substrate;

a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising;

a doped layer over the substrate;

a dielectric layer over the doped layer; and

a conductive fill material over the dielectric layer;

a first conductive contact from the first transistor structure to a first bit line;

a second conductive contact from the second transistor to a non-volatile memory element; and

a third conductive contact from the non-volatile memory element to a second bit line.

16. The semiconductor device of claim 15, wherein the doped layer is electrically coupled to a source/drain portion of the first transistor structure and to a source/drain portion of the second transistor structure.

17. The semiconductor device of claim 15, wherein the capacitor structure further comprises a conductive cap structure over the conductive fill material.

18. The semiconductor device of claim 15, wherein the first conductive contact comprises:

a first via electrically coupled to a source/drain region of the first transistor;

a second via electrically coupled to the first bit line; and

a first portion of a first metal layer electrically coupled to the first and second vias.

19. The semiconductor device of claim 18, wherein the second conductive contact comprises:

a first via electrically coupled to a source/drain region of the second transistor;

a second via;

a second portion of the first metal layer electrically coupled to the first and second vias;

a third via; and

a portion of a second metal layer electrically coupled to the second and third vias.

20. The semiconductor device of claim 15, wherein the non-volatile memory element comprises a variable resistive element, the variable resistive element selected from one of a group consisting of:

a resistive random access memory element, a magnetic random access memory element, a phase-change memory resistive element, and a carbon nanotube resistive element.