Method of Forming a Transistor, Method of Patterning a Substrate, and Transistor

• US 20160093706A1
• Filed: 09/25/2015
• Published: 03/31/2016
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Santos Rodriguez, Francisco Javier, Brandt, Philip Christoph, Stegner, Andre Rainer
• Granted Patent: US 9,954,068 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.

Claims

1. A method of forming a transistor including a gate electrode, the method comprising:

forming a sacrificial layer over a semiconductor substrate;

forming a patterning layer over the sacrificial layer;

patterning the patterning layer to form patterned structures;

forming spacers adjacent to sidewalls of the patterned structures;

removing the patterned structures;

etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate; and

filling a conductive material in the trenches in the semiconductor substrate to form gate electrodes.

2. The method of claim 1, wherein etching through the sacrificial layer and etching into the substrate also forms first through holes in the sacrificial layer, and wherein the conductive material also fills the first through holes in the sacrificial layer.

3. The method of claim 1, further comprising forming a hard mask layer over the semiconductor substrate before forming the sacrificial layer, the sacrificial layer being selectively etchable with respect to the hard mask layer.

4. The method of claim 3, further comprising etching through the hard mask layer using the patterned sacrificial layer as an etching mask to form second through holes in the hard mask layer and to form patterned hardmask portions, and wherein the conductive material also fills the second through holes in the hard mask layer.

5. The method of claim 4, further comprising covering an edge portion of the semiconductor substrate with portions of a resist material before etching so that the spacers and the portions of the resist material act as the etching mask.

6. The method of claim 2, further comprising modifying a surface portion of the conductive material to form modified surface portions.

7. The method of claim 4, further comprising covering sidewalls of the patterned hardmask with a cover layer.

8. The method of claim 6, wherein modifying the surface portion of the conductive material comprises oxidizing the surface of the conductive material.

9. The method of claim 1, further comprising forming a gate contact to the gate electrode, by defining an opening in a photoresist material over the semiconductor substrate, the opening having a greater width than a width of the trench.

10. The method of claim 1, further comprising forming a mesa contact to the semiconductor substrate material between adjacent trenches, by defining an opening in a photoresist material over the semiconductor substrate, the opening having a greater width than a distance between adjacent trenches.

11. The method of claim 1, further comprising forming a dielectric layer on a sidewall of the trench in the semiconductor substrate before filling the conductive material in the trenches.

12. The method of claim 1, further comprising forming components of a power device selected from the group consisting of insulated gate bipolar transistors, diodes, and field effect transistors.

13. The method of claim 1, further comprising forming mesa contacts to the semiconductor substrate between adjacent trenches and forming a conductive element electrically coupling the mesa contacts to each other.

14. The method of claim 1, further comprising forming gate contacts to the gate electrodes and forming a conductive element electrically coupling the gate contacts to each other.

15. A method for patterning a substrate, the method comprising:

forming a sacrificial layer over the substrate;

forming a patterning layer over the sacrificial layer;

patterning the patterning layer to form patterned structures;

forming spacers adjacent to sidewalls of the patterned structures;

removing the patterned structures;

etching through the sacrificial layer using the spacers as an etching mask and etching into the substrate, thereby forming first through holes in the sacrificial layer and trenches in the substrate; and

filling a fill material into the trenches in the substrate and in the first through holes in the sacrificial layer.

16. The method of claim 15, further comprising modifying a surface of the fill material to form modified surface portions.

17. The method of claim 16, wherein modifying the surface of the fill material comprises oxidizing the surface of the fill material.

18. The method of claim 15, wherein forming the trenches in the substrate and the first through holes in the sacrificial layer comprises:

etching the sacrificial layer using the spacers as an etching mask to form the first through holes and sacrificial structures in the sacrificial layer;

removing the spacers; and

etching the trenches into the substrate using the sacrificial structures as an etching mask.

19. The method of claim 18, further comprising forming a cover layer on sidewalls of the sacrificial structures before etching the trenches into the substrate.

20. A transistor comprising trenches in a semiconductor substrate, a gate electrode arranged in the trenches and mesas defined between adjacent trenches,

wherein the gate electrode comprises a first portion disposed over a main surface of the substrate and a second portion disposed below the main surface,

wherein a width of the first portion of the gate electrode is greater than a diameter of the second portion of the gate electrode, and

wherein a width of the mesas is between 50 to 500 nm.