Method of Manufacturing a Semiconductor Device and Semiconductor Device

• US 20160093731A1
• Filed: 09/29/2015
• Published: 03/31/2016
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas, Schloesser, Till
• Granted Patent: US 9,530,884 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of manufacturing a semiconductor device including a transistor comprises forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches, forming a field dielectric layer in the field plate trenches, thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches, and forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches. The method further comprising forming a source region and forming a drain region in the main surface of the semiconductor substrate.

Claims

1. A method of manufacturing a semiconductor device including a transistor, comprising:

forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches;

forming a field dielectric layer in the field plate trenches;

thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches; and

forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches,

the method further comprising forming a source region and forming a drain region in the main surface of the semiconductor substrate.

2. The method according to claim 1, wherein the source region and the drain region are arranged along a first horizontal direction, the field plate trenches and the gate trenches are formed between the source region and the drain region, at least one of the field plate trenches and at least one of the gate trenches being arranged along the first horizontal direction.

3. The method according to claim 1, further comprising forming a source contact in contact with the source region, wherein forming the source contact comprises forming a source contact groove in the main surface.

4. The method according to claim 3, wherein the source contact groove is formed in a self-aligned manner with respect to the gate trenches.

5. The method according to claim 3, wherein the source contact groove and the gate trenches are formed by a joint etching process.

6. The method according to claim 3, wherein the source contact groove and the gate trenches extend to approximately the same depth.

7. The method according to claim 1, further comprising doping the channel region.

8. The method according to claim 7, wherein the doping process for forming the channel region is performed before forming the field plate trenches.

9. The method according to claim 7, wherein the doping process for forming the channel region is performed after forming the gate trenches and before forming the conductive material in the gate trenches.

10. The method according to claim 7, wherein the doping process for forming the channel region is performed after forming the conductive material in the gate trenches.

11. The method according to claim 10, wherein the doping process for forming the channel region comprises a tilted ion implantation process.

12. The method according to claim 11, wherein the tilted ion implantation process is followed by a further tilted ion implantation process for defining a source region.

13. The method according to claim 1, wherein each of the field plate trenches and each of the gate trenches is formed to extend in the first horizontal direction, adjacent ones of the field plate trenches and of the gate trenches being disposed along a second horizontal direction perpendicular to the first direction.

14. The method according to claim 13, wherein a width d of the channel region (220) formed between adjacent gate trenches fulfills d≦

2×

ld, wherein ld denotes a length of a depletion zone formed at an interface between the channel region and the gate electrode, the width d being measured in a horizontal direction perpendicular to the first direction.

15. A method of manufacturing a semiconductor device including a transistor, comprising:

forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches;

forming a field dielectric layer in the field plate trenches;

thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches; and

forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches,

wherein each of the field plate trenches and each of the gate trenches is formed to extend in the first horizontal direction, adjacent ones of the field plate trenches and of the gate trenches being disposed along a second horizontal direction perpendicular to the first direction.

16. A semiconductor device comprising a transistor including:

field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches;

a dielectric layer at sidewalls of the field plate trenches;

gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches; and

a conductive material in at least some of the field plate trenches and in at least some of the gate trenches,

wherein the channel region is defined in the semiconductor substrate between adjacent gate trenches, the dielectric layer being disposed over an upper surface of the channel region, the semiconductor device further comprising a source region and a drain region in the main surface.

17. The semiconductor device according to claim 16, further comprising a source region and a source contact in contact with the source region, the source contact being disposed in a source contact groove in the main surface.

18. The semiconductor device according to claim 17, wherein the source contact groove and the gate trenches extend to approximately the same depth.

19. The semiconductor device according to claim 16, wherein each of the field plate trenches and each of the gate trenches extends in a first horizontal direction, adjacent ones of the field plate trenches and of the gate trenches being disposed along a second horizontal direction perpendicular to the first direction.

20. The semiconductor device according to claim 19, wherein a width d of the channel region formed between adjacent gate trenches fulfills d≦

2×

ld, wherein ld denotes a length of a depletion zone formed at an interface between the channel region and the gate electrode, the width d being measured in a horizontal direction perpendicular to the first direction.