SUPPLY-MODULATION CROSS DOMAIN DATA INTERFACE

• US 20160094225A1
• Filed: 09/30/2014
• Published: 03/31/2016
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: LIM, Shao-Jen, SHAMARAO, Prashant
• Granted Patent: US 9,509,308 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2203/04103 Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 5/02 by amplifying H03K5/04 takes precedence

Abstract

A method for converting data signals from one power supply voltage domain for use in another power supply voltage domain. The method includes receiving the data signal at a first node of the integrated circuit, wherein the first node is within the first power supply voltage domain. The method also includes generating a first intermediate differential signal from the data signal via a first conversion circuit of the integrated circuit. The method further includes communicating the first intermediate differential signal to a first cross-coupled latch, wherein the first cross-coupled latch generates a first output signal based on the first intermediate differential signal. The method also includes outputting the first output signal from a second node of the integrated circuit, wherein the second node is in the second power supply voltage domain. Other embodiments, such as an integrated circuit, and an input device, are also provided.

Claims

1. A method for communicating a data signal within an integrated circuit of a processing system having a first power supply voltage domain and a second power supply voltage domain, wherein at least one of a positive power supply voltage of the second power supply voltage domain and a negative power supply voltage of the second power supply voltage domain are modulated with respect to the first power supply voltage domain, the method comprising:

receiving the data signal at a first node of the integrated circuit, wherein the first node is within the first power supply voltage domain;

generating a first intermediate differential signal from the data signal via a first conversion circuit of the integrated circuit;

communicating the first intermediate differential signal to a first cross-coupled latch, wherein the first cross-coupled latch generates a first output signal based on the first intermediate differential signal; and

outputting the first output signal from a second node of the integrated circuit, wherein the second node is in the second power supply voltage domain.

2. The method of claim 1, wherein communicating the first intermediate differential signal to the first cross-coupled latch comprises communicating the first intermediate differential signal to the first cross-coupled latch that is coupled to the positive power supply voltage of the second power supply voltage domain.

3. The method of claim 2, wherein:

the positive power supply voltage of the second power supply voltage domain does not drop below the positive power supply voltage of the first power supply voltage domain; and

the negative power supply voltage of the second power supply voltage domain does not drop below the negative power supply voltage of the first power supply voltage domain.

4. The method of claim 1, wherein communicating the first intermediate differential signal to the first cross-coupled latch comprises communicating the first intermediate differential signal to the first cross-coupled latch that is coupled to the negative power supply voltage of the second power supply voltage domain.

5. The method of claim 4, wherein:

the positive power supply voltage of the second power supply voltage domain does not rise above the positive power supply voltage of the first power supply voltage domain; and

the negative power supply voltage of the second power supply voltage domain does not rise above the negative power supply voltage of the first power supply voltage domain.

6. The method of claim 1, wherein:

generating the first intermediate differential signal from the data signal comprises transmitting the data signal through a pair of alternating-current couplings to generate the first intermediate differential signal.

7. The method of claim 1, wherein generating the first intermediate differential signal comprises removing effects corresponding to modulation in at least one of the positive power supply voltage of the second power supply voltage domain and the negative power supply voltage of the second power supply voltage domain.

8. The method of claim 7, wherein removing effects corresponding to at least one of the positive power supply voltage of the second power supply voltage domain and the negative power supply voltage of the second power supply voltage domain comprises:

communicating the data signal through a pair of cascode transistors coupled in series with a differential pair to generate the first intermediate differential signal.

9. The method of claim 1 wherein communicating the first intermediate differential signal to the first cross-coupled latch further comprises:

communicating the first intermediate differential signal to a first current mirror configured to generate a first current mirror signal based on the first intermediate differential signal; and

generating the first output signal based on the first current mirror signal.

10. The method of claim 9, wherein communicating the first intermediate differential signal to the first cross-coupled latch further comprises:

communicating the first intermediate differential signal to a second current mirror configured to generate a second current mirror signal based on the first intermediate differential signal, wherein the second current mirror signal is a logical inverse of the first current mirror signal; and

communicating the first current mirror signal to a first inverter having a first output that is coupled, through a first resistor, to the second current mirror signal.

11. An integrated circuit comprising:

a first power supply voltage domain;

a second power supply voltage domain, wherein at least one of a positive power supply voltage of the second power supply voltage domain and a negative power supply voltage of the second power supply voltage domain are modulated with respect to the first power supply voltage domain; and

a cross-domain interface circuit, comprising;

a first conversion circuit that includes a first node and that is within the first power supply voltage domain, and

a second conversion circuit that is within the second power supply voltage domain and that includes a second node and a first cross-coupled latch,

wherein the first conversion circuit is configured to receive a data signal at the first node, generate a first intermediate differential signal from the data signal, and communicate the first intermediate differential signal to the second conversion circuit; and

wherein the second conversion circuit is configured to receive the first intermediate differential signal at the first cross-coupled latch, generate a first output signal based on the first intermediate differential signal via the first cross-coupled latch, and output the first output signal from the second node.

12. The integrated circuit of claim 11, wherein:

the first cross-coupled latch is coupled to a positive power supply voltage of the second power supply voltage domain.

13. The integrated circuit of claim 12, wherein:

the positive power supply voltage of the second power supply voltage domain does not drop below the positive power supply voltage of the first power supply voltage domain; and

the negative power supply voltage of the second power supply voltage domain does not drop below the negative power supply voltage of the first power supply voltage domain.

14. The integrated circuit of claim 11, wherein:

the first cross-coupled latch is coupled to a negative power supply voltage of the second power supply voltage domain.

15. The integrated circuit of claim 14, wherein:

the positive power supply voltage of the second power supply voltage domain does not rise above a positive power supply voltage of the first power supply voltage domain; and

the negative power supply voltage of the second power supply voltage domain does not rise above the negative power supply voltage of the first power supply voltage domain.

16. The integrated circuit of claim 11, wherein:

the first conversion circuit includes a pair of cascode transistors configured to receive the data signal and coupled in series with a differential pair to generate the first intermediate differential signal.

17. The integrated circuit of claim 11, wherein:

the second conversion circuit includes a first current mirror configured to generate a first current mirror signal based on the first intermediate differential signal, and

the second conversion circuit is configured to generate the first output signal based on the first current mirror signal.

18. The integrated circuit of claim 17, wherein:

the second conversion circuit further includes;

a second current mirror configured to generate a second current mirror signal based on the first intermediate differential signal, wherein the second current mirror signal is a logical inverse of the first current mirror signal,

a first resistor, and

a first inverter having an output coupled to the first resistor and an input configured to receive the first current mirror signal,

wherein the first resistor is configured to receive the second current mirror signal.

19. The integrated circuit of claim 11, wherein:

the first conversion circuit further includes a pair of alternating-current couplings configured to generate the first intermediate differential signal based on the data signal.

20. The integrated circuit of claim 11, wherein the first conversion circuit further comprises:

a controlled-current source; and

a differential pair of transistors,

wherein a source of each of the differential pair of transistors is coupled to the negative power supply voltage of the first power supply voltage domain through the controlled-current source.

21. The integrated circuit of claim 11, wherein the first intermediate differential signal is in the first power supply voltage domain and wherein the first intermediate differential signal is converted into a second intermediate differential signal in the second power supply voltage domain by the first cross-coupled latch.

22. The integrated circuit of claim 21, wherein the second conversion circuit further comprises:

a first differential current source configured to receive the second intermediate differential signal;

a first pair of current mirror sources coupled in parallel with the first differential current source, wherein the first differential current source is configured to cause the first pair of current mirror sources to conduct a first current mirror signal;

a first pair of current mirror sinks configured to sink current to the negative power supply voltage of the second power supply voltage domain;

a second cross-coupled latch that is coupled to the negative power supply voltage of the second power supply voltage domain,

wherein the first pair of current mirror sources is configured to drive the second cross-coupled latch and the first pair of current mirror sinks.

23. The integrated circuit of claim 22, wherein the second conversion circuit further comprises:

a first pair of buffering inverters coupled to a positive output node,

wherein both the first pair of current mirror sources and the first pair of current mirror sinks are coupled to the first pair of buffering inverters.

24. The integrated circuit of claim 23, wherein the second conversion circuit further comprises:

a second differential current source configured to receive the second intermediate differential signal;

a second pair of current mirror sources coupled in parallel with the second differential current source, wherein the second differential current source is configured to cause the second pair of current mirror sources to conduct a second current mirror signal;

a second pair of current mirror sinks configured to sink current to the negative power supply voltage of the second power supply voltage domain,

wherein the second pair of current mirror sources is configured to drive the second cross-coupled latch and the second pair of current mirror sinks.

25. The integrated circuit of claim 24, wherein the second conversion circuit further comprises:

a second pair of buffering inverters coupled to a negative output node,

wherein both the second pair of current mirror sources and the second pair of current mirror sinks are coupled to the second pair of buffering inverters.

26. The integrated circuit of claim 25, wherein:

the first pair of buffering inverters is cross-coupled to the second pair of buffering inverters with a pair of resistors.

27. The integrated circuit of claim 21, wherein the second conversion circuit further comprises:

a first differential current sink configured to receive the second intermediate differential signal;

a first pair of current mirror sinks coupled in parallel with the first differential current sink, wherein the first differential current sink is configured to cause the first pair of current mirror sinks to conduct a first current mirror signal;

a first pair of current mirror sources configured to source current from the positive power supply voltage of the second power supply voltage domain;

a second cross-coupled latch that is coupled to the positive power supply voltage of the second power supply voltage domain,

wherein the first pair of current mirror sinks is configured to drive the second cross-coupled latch and the first pair of current mirror sources.

28. The integrated circuit of claim 27, wherein the second conversion circuit further comprises:

a first pair of buffering inverters coupled to a positive output node,

wherein both the first pair of current mirror sources and the first pair of current mirror sinks are coupled to the first pair of buffering inverters.

29. The integrated circuit of claim 28, wherein the second conversion circuit further comprises:

a second differential current sink configured to receive the second intermediate differential signal;

a second pair of current mirror sinks coupled in parallel with the second differential current sink, wherein the second differential current sink is configured to cause the second pair of current mirror sinks to conduct a second current mirror signal;

a second pair of current mirror sources configured to source current from the positive power supply voltage of the second power supply voltage domain,

wherein the second pair of current mirror sinks is configured to drive the second cross-coupled latch and the second pair of current mirror sources.

30. The integrated circuit of claim 29, wherein the second conversion circuit further comprises:

a second pair of buffering inverters coupled to a negative output node,

wherein both the second pair of current mirror sources and the second pair of current mirror sinks are coupled to the second pair of buffering inverters.

31. The integrated circuit of claim 30, wherein:

the first pair of buffering inverters is cross-coupled to the second pair of buffering inverters with a pair of resistors.

32. An input device, comprising:

a plurality of sensor electrodes; and

a processing system configured to drive the plurality of sensor electrodes for capacitive sensing, the processing system including an integrated circuit comprising;

a first power supply voltage domain;

a second power supply voltage domain, wherein at least one of a positive power supply voltage of the second power supply voltage domain and a negative power supply voltage of the second power supply voltage domain are modulated with respect to the first power supply voltage domain; and

a cross-domain interface circuit, comprising;

a first conversion circuit that includes a first node and that is within the first power supply voltage domain, and

a second conversion circuit that is within the second power supply voltage domain and that includes a second node and a first cross-coupled latch,

wherein the first conversion circuit is configured to receive a data signal at the first node, generate a first intermediate differential signal from the data signal, and communicate the first intermediate differential signal to the second conversion circuit; and

wherein the second conversion circuit is configured to receive the first intermediate differential signal at the first cross-coupled latch, generate a first output signal based on the first intermediate differential signal via the first cross-coupled latch, and output the first output signal from the second node.