RELAXED DIGITIZATION SYSTEM LINEARIZATION

• US 20160094253A1
• Filed: 05/20/2014
• Published: 03/31/2016
• Est. Priority Date: 05/20/2013
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: WEBER, THEOPHANE, McCORMICK, MARTIN STEVEN, MENG, QINGDONG
• Granted Patent: US 9,595,982 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception

Abstract

An approach to linearization relaxes the requirements on the digitization of the analog output signal while maintaining the benefits of a high sampling rate of the output signal. The digitization approach extracts sufficient information to characterize the output signal over a wide bandwidth without necessarily determining sufficient information to fully represent the output signal, for example, without sampling the output signal at the Nyquist sampling rate with a sufficient precision to accurately represent the signal.

Claims

1. A digital predistortion linearizer, comprising:

a first input to receive an input signal representative of a desired output from a plant, the desired output having a desired output bandwidth;

a configurable pre-distorter to determine a driving signal representative of an input to the plant to achieve the desired output from the plant, the driving signal having a driving signal data rate equal to a product of a driving signal sampling rate and a driving signal precision;

a first output to provide an output signal representative of the driving;

a second input to receive an analog sensor signal representative of an achieved output from the plant;

a sampler coupled to the second input to process the analog sensor signal, wherein the sampler is responsive to components of the analog sensor signal outside the desired output bandwidth in a sensor bandwidth greater than the desired output bandwidth, the sampler includes an analog to digital converter (ADC) coupled to the second input, the ADC is to provide digital outputs at a sensor signal precision lower than the driving signal precision, and the sampler is to provide a sampled sensor signal having a sensor signal data rate smaller than the driving signal data rate; and

an estimator to receive the sampled sensor signal from the sampler and the driving signal determined by the pre-distorter, and to provide configuration data for configuring the pre-distorter.

6. The digital predistortion linearizer of claim 1, wherein the ADC is to provide digital outputs at a sensor signal sampling rate lower than the driving signal sampling rate.

7. The digital predistortion linearizer of claim 1, wherein the sampler comprises:

a sampling circuit responsive to signal components of the analog sensor signal outside the desired output bandwidth, and to acquire analog samples of the analog sensor signal at a sensor sampling rate insufficient to represent the sensor bandwidth;

wherein the ADC is to convert the acquired analog samples to form the digitized sampled sensor signal, and the digitized sampled sensor signal is representative of at least some signal components outside the desired output bandwidth.

9. The digital predistortion linearizer of claim 1, wherein the ADC comprises a quantizer, a difference element to receive the analog sensor signal and produce a difference between the analog sensor signal and an output of the quantizer, and a filter coupled between the difference element and the quantizer to provide a filter output of the difference element to the quantizer, and wherein the digitized sampled sensor signal is determined by an output of the quantizer.

10. The digital predistortion linearizer of claim 1, wherein the sampler comprises a subband sampler configurable to quantize a subband within the sensor bandwidth, the subband having a bandwidth smaller than the sensor bandwidth, and wherein the ADC is to provide sampled sensor values at a sampling rate sufficient to represent the subband bandwith.

2. The digital predistortion linearizer of claim 0, wherein the plant comprises a radio frequency amplifier.

3. The digital predistortion linearizer of claim 0, wherein the digital predistortion linearizer is operatively coupled to the plant.

4. The digital predistortion linearizer of claim 0, further comprising:

a digital to analog converter (DAC) coupled between the pre-distorter and the first output, wherein the output signal comprises an analog signal output from the DAC, and the DAC is to convert the driving signal precision to analog form at the driving signal sampling rate.

5. (canceled)

8. (canceled)

11. The digital predistortion linearizer of claim 0, wherein the estimator is to use sampled sensor signals from a plurality of subbands to determine the configuration for the pre-distorter.

12. The digital predistortion linearizer of claim 0, wherein the digital predistortion linearizer is integrated into a single integrated circuit device.

13. The digital predistortion linearizer of claim 0, comprising a controller and a memory to store instructions and data for configuring the digital predistortion linearizer.

14. A method for linearization of a plant, comprising:

receiving an input signal representative of a desired output from the plant, the desired output having a desired output bandwidth;

determining, according to pre-distorter configuration data, a driving signal representative of an input to the plant to achieve the desired output from the plant, the driving signal having a driving signal data rate equal to a product of a driving signal sampling rate and a driving signal precision;

providing an output signal representative of the driving signal to the plant, wherein providing the output signal comprises converting the driving signal using a digital to analog converter (DAC) at the driving signal sampling rate and the driving signal precision;

receiving a sensor input signal representative of an achieved output from the plant;

processing the sensor input signal to determine sampled sensor data, said processing being responsive to components of the sensor input signal outside the desired output bandwidth in a sensor bandwidth greater than the desired output bandwidth, wherein the sampled sensor data has a data rate smaller than the driving signal data rate, and wherein processing the sensor input signal comprises determining digital outputs at a sensor signal precision less than the driving signal precision; and

determining the pre-distorter configuration data from the sampled sensor data and the driving signal.

19. The method of claim 14, wherein the sensor signal precision is smaller than one half the driving signal precision.

20. The method of claim 14, wherein determining the digital outputs comprises applying a Delta-Sigma (Δ

Σ

) conversion approach to the sensor signal.

15. (canceled)

16. The method of claim 0, wherein processing the sensor input signal comprises determining digital outputs at a sensor signal sampling rate lower than the driving signal sampling rate.

17. The method of claim 0, wherein determining the digital outputs comprises sampling using analog circuitry suitable for processing of the sensor signal at the sensor bandwidth and converting the sensor signal to form the digital outputs at a conversion rate lower smaller the sensor bandwidth.

18. The method of claim 0, wherein determining the digital outputs comprises in a succession of time intervals, forming the digital outputs to represent different subbands smaller than the sensor bandwidth, and wherein determining the pre-distorter configuration data comprises combining the digital outputs from a plurality of the subbands.

21. A linearization system, comprising:

a signal sampling apparatus, comprising;

a first component including an input to receive a first signal representative of an output of a plant, and an output to provide a second signal representative of the first signal, the second signal having a second bandwidth,

a second component coupled to the first component to sample the second signal at a second rate smaller than a sampling rate sufficient to represent the second signal, and

an analog to digital converter (ADC), coupled to the second component, to convert the samples of the second signal;

an estimator, coupled to the signal sampling apparatus, to receive digitally converted samples of the second signal, to receive samples of a driving signal to the plant, and to determine data characterizing non-linear characteristics of the plant, wherein the driving signal has a driving signal signal data rate equal to a product of a driving signal sampling rate and a driving signal precision; and

a predistorter to receive the data characterizing the non-linear characteristics and a desired signal, and to provide the input signal to the plant;

wherein the ADC is to provide digital outputs at a precision lower than the driving signal precision.

22. The linearization system of claim 21, wherein the predistorter includes:

an output predictor to receive the data characterizing the non-linear characteristics and samples of the input signal, and to determine estimated output samples of the amplifier; and

an input estimator to receive samples of the desired output signal, and to determine the input signal for the plant.

23. The linearization system of claim 0, wherein the plant comprises a power amplifier.

24. The linearization system of claim 0, wherein the plant comprises a modulator to receive the input signal to the plant, and to provide a modulated radio frequency signal to the power amplifier.

25. The linearization system of claim 0, wherein the plant further comprises a demodulator to provide the second signal as a demodulation of an output of the power amplifier.

26. The linearization system of claim 0, wherein the second signal comprises a modulated output of the power amplifier, and the second component is to perform a direct conversion of the second signal.

27. (canceled)

28. The linearization system of claim 0, wherein the second signal comprises multiple components, and the ADC is to be shared to convert samples of said components at different times.

29. The linearization system of claim 0, wherein the multiple components comprise quadrature components.

30. (canceled)