INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY

• US 20160094340A1
• Filed: 09/26/2014
• Published: 03/31/2016
• Est. Priority Date: 09/26/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wolrich, Gilbert M., Gulley, Sean M., Gopal, Vinodh, Feghali, Wajdi K., Yap, Kirk S.
• Granted Patent: US 9,467,279 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3895 for complex operations, e.g. multidimensional or interleaved address generators, macros
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/24 Key scheduling, i.e. generating round keys or sub-keys for block encryption
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
• CPC Class Codes: H04L 9/0869 involving random numbers or seeds

Abstract

Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Claims

1. A processor comprising:

a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) SM4 operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and

one or more execution units, responsive to the decoded first instruction, to;

perform one or more SM4-round exchange of a portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set if a first indicator of said one or more substitution function indicators indicates a first substitution function;

perform one or more SM4 key generation using said portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set if a second indicator of said one or more substitution function indicators indicates a second substitution function; and

store a result of the first instruction in a SIMD destination register.

2. The processor of claim 1, wherein said first substitution function is the SM4 mixer-substitution function, T.

3. The processor of claim 2, wherein said second substitution function is the SM4 key expansion substitution function, T′

.

4. The processor of claim 1, wherein the first instruction specifies said SIMD destination register as a destination operand.

5. The processor of claim 1, wherein the first instruction specifies a SIMD register to hold four 32-bit elements as the first source data operand set.

6. The processor of claim 1, wherein the first instruction specifies a SIMD register to hold eight 32-bit elements as the first source data operand set.

7. The processor of claim 1, wherein the first instruction specifies a SIMD register to hold sixteen 32-bit elements as the first source data operand set.

8. The processor of claim 1, wherein the first instruction specifies said one or more substitution function indicators as an immediate byte operand.

9. The processor of claim 8, wherein the first instruction specifies said one or more substitution function indicators by setting one bit in the immediate byte operand for each corresponding lane of four 32-bit elements in the first source data operand set.

10. The processor of claim 1, wherein the first instruction specifies said one or more substitution function indicators in the first instruction mnemonic.

11. The processor of claim 1, wherein said one or more execution units, responsive to the decoded first instruction, performs four SM4-round exchanges of, or four SM4 key generation using said portion of the first source data operand set.

12. A machine-readable medium to record functional descriptive material having stored thereon one or more executable instructions including a first instruction, which if executed on behalf of a thread of a machine causes the machine to:

access a first source data operand set of elements, a second source data operand set of elements, and one or more substitution function indicators;

perform a first one or more SM4-round exchange of a portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function;

perform a first one or more SM4 key generation using said portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function; and

store a set of result elements of the one or more SM4-round exchange and the one or more SM4 key generation in a SIMD register.

13. The machine-readable medium of claim 12, said one or more executable instructions also including a second instruction, which if executed on behalf of the thread of said machine further causes the machine to:

access the set of result elements of the one or more SM4-round exchange and the one or more SM4 key generation in the SIMD register, a third source data operand set of elements, and another one or more substitution function indicators;

perform a second one or more SM4-round exchange of a portion of the set of result elements with a corresponding second one or more keys from the third source data operand set in response to a third indicator of said another one or more substitution function indicators that indicates the first substitution function;

perform a second one or more SM4 key generation using said portion of the set of result elements with a corresponding second one or more constants from the third source data operand set in response to a fourth indicator of said another one or more substitution function indicators that indicates the second substitution function; and

store another set of result elements of the second one or more SM4-round exchange and second one or more SM4 key generation in the SIMD register.

14. The machine-readable medium of claim 13, wherein said first substitution function is the SM4 mixer-substitution function, T.

15. The machine-readable medium of claim 14, wherein said second substitution function is the SM4 key expansion substitution function, T′

.

16. The machine-readable medium of claim 15, said one or more executable instructions, if executed on behalf of the thread of said machine further causes the machine to:

store, in a second SIMD register, the third source data operand set of elements; and

repeat execution of said second instruction on behalf of the thread of said machine.

17. The machine-readable medium of claim 16, wherein said one or more executable instructions, if executed on behalf of the thread of said machine cause said storing in the second SIMD register and repeating of the execution of said second instruction until at least thirty-two SM4-round exchanges and SM4 key generations are performed on behalf of the thread of said machine.

18. The machine-readable medium of claim 17, wherein said one or more executable instructions, if executed on behalf of the thread of said machine cause said repeating of the execution of said second instruction not more than fifteen times after execution of the first instruction to complete the thirty-two SM4-round exchanges and SM4 key generations on behalf of the thread of said machine.

19. The machine-readable medium of claim 18, wherein said one or more executable instructions, if executed on behalf of the thread of said machine cause said repeating of the execution of said second instruction only seven times after execution of the first instruction to complete the thirty-two SM4-round exchanges and SM4 key generations on behalf of the thread of said machine.

20. A method comprising:

decoding a first instruction for a Single Instruction Multiple Data (SIMD) SM4 round slice operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and

responsive to the first instruction,

accessing the first source data operand set,

accessing the second source data operand set,

performing a first plurality of SM4-round exchanges on a first portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function,

performing the first plurality of SM4 key generations using a second portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function, and

storing a set of result elements of the first instruction in a SIMD destination register.

21. The method of claim 20 further comprising:

generating a plurality of micro-instructions equal to said first plurality responsive to the first instruction.

22. The method of claim 20, wherein the first plurality is equal to four.

23. The method of claim 20, wherein the first plurality is equal to two.

24. The method of claim 20, wherein said first and second portions comprise 128-bit wide SIMD data lanes.

25. The method of claim 20, wherein said first substitution function is the SM4 mixer-substitution function, T.

26. The method of claim 25, wherein said second substitution function is the SM4 key expansion substitution function, T′

.

27. A processing system comprising:

a memory to store a first instruction for a Single Instruction Multiple Data (SIMD) SM4 round slice operation; and

a processor comprising;

an instruction fetch stage to fetch the first instruction;

a decode stage to decode a first instruction, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and

one or more execution units, responsive to the decoded first instruction, to;

access the first source data operand set,

access the second source data operand set,

perform a first plurality of SM4-round exchanges on a first portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function,

perform the first plurality of SM4 key generations using a second portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function, and

store a set of result elements of the first instruction in a SIMD destination register.

28. The processing system of claim 27, wherein said first substitution function is the SM4 mixer-substitution function, T.

29. The processing system of claim 28, wherein said second substitution function is the SM4 key expansion substitution function, T′

.

30. The processing system of claim 27, wherein said decode stage, responsive to decoding the first instruction, is further to:

generate a plurality of micro-instructions equal to said first plurality responsive to the first instruction.

31. The processing system of claim 27, wherein the first plurality is equal to four.

32. The processing system of claim 27, wherein the first plurality is equal to two.

33. The processing system of claim 27, wherein said first and second portions comprise 128-bit wide SIMD data lanes.

34. A apparatus in a processor comprising:

a memory to store a first instruction for a Single Instruction Multiple Data (SIMD) SM4 round slice operation, the first instruction specifying a first source data operand set, a second source data operand set, and one or more substitution function indicators; and

a processor comprising;

one or more encryption units, responsive to the first instruction, to;

perform a first plurality of SM4-round exchanges on a first portion of the first source data operand set with a corresponding first one or more keys from the second source data operand set in response to a first indicator of said one or more substitution function indicators that indicates a first substitution function,

perform the first plurality of SM4 key generations using a second portion of the first source data operand set with a corresponding first one or more constants from the second source data operand set in response to a second indicator of said one or more substitution function indicators that indicates a second substitution function, and

store a set of result elements of the first instruction in a SIMD destination register.

35. The apparatus of claim 34, wherein the first instruction specifies said SIMD destination register as a destination operand.

36. The apparatus of claim 34, wherein the first instruction specifies said SIMD destination register as the first source data operand.

37. The apparatus of claim 34, wherein the first instruction specifies said one or more substitution function indicators as an immediate data operand.