METHOD AND APPARATUS FOR SEGMENTED SEQUENTIAL STORAGE

• US 20160098279A1
• Filed: 10/22/2015
• Published: 04/07/2016
• Est. Priority Date: 08/29/2005
• Status: Abandoned Application

• Current Assignee: RPX Corporation
• Original Assignee: Searete LLC (Intellectual Ventures LLC)
• Inventors: Glew, Andrew F.
• Application Number:
  US14/920,590
• Publication Number:
  US 20160098279A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

Various embodiments are described relating to processors, hierarchical processors, branch predictors, branch prediction systems, and computing systems. Some or all of a hierarchical instruction scheduler, hierarchical register file, or a hierarchical store buffer may be included in a hierarchical microprocessor. Some or all aspects of the hierarchical microprocessor may be implemented, partially or fully, using a method for sequential data storage.

Claims

1. (canceled)

2. A processor comprising:

a plurality of branch predictors, wherein each branch predictor is adapted to provide a prediction and an override signal; and

a branch prediction control circuit adapted to generate a branch prediction based on the prediction and the override signal from each predictor,

wherein the override signal of a particular predictor results in one of (i) the prediction of the particular predictor being accepted by the processor regardless of the predictions of the other predictors and (ii) the prediction of the particular predictor not being accepted by the processor regardless of the prediction of the particular predictor.

3. The processor of claim 2 wherein each branch predictor is adapted to provide a prediction, an override signal and a confidence level.

4. The processor of claim 2 wherein the override signal of each branch predictor includes a respective positive override signal indicating that a prediction of a particular branch predictor of the plurality of branch predictors asserting its positive override signal should be accepted by the processor regardless of the predictions of the other branch predictors of the plurality of branch predictors.

5. The processor of claim 2 wherein the override signal of each branch predictor includes a respective negative override signal indicating that a prediction of a particular branch predictor of the plurality of branch predictor asserting its negative override signal should not be accepted by the processor.

6-25. -25. (canceled)

26. A method for processing instructions in a microprocessor, the method comprising:

receiving instructions for execution at a first-level instruction scheduler;

storing first operand status information for respective operands of the instructions;

dispatching, based on the first operand status information, the instructions to respective execution clusters of the microprocessor, wherein each of the respective execution clusters includes a corresponding second-level instruction scheduler, the second-level instruction schedulers being operatively coupled with the first-level instruction scheduler;

receiving, at the second-level instruction schedulers, the instructions from the first-level instruction scheduler;

storing second operand status information for respective operands of the instructions;

dispatching, based on the second operand status information, the instructions to respective execution units of the execution clusters; and

executing one of more of the instructions.

27. The method of claim 26, further comprising:

assigning an execution thread to a single execution cluster; and

dispatching instructions associated with the execution thread to the single execution cluster.

28. The method of claim 26, wherein dispatching the instructions from the first-level instruction scheduler includes dispatching the instructions in accordance with a load balancing policy.

29. The method of claim 26, further comprising assigning a spawned thread to an execution cluster different than an execution cluster executing an associated spawning thread.

30-100. -100. (canceled)

101. An apparatus comprising a non-transitory machine readable medium having instructions stored thereon, the instructions, when executed by a processor, provide for at least:

dividing a non-circular data structure into a plurality of segments, each segment including a plurality of entries;

dynamically allocating the plurality of segments; and

sequentially associating the dynamically allocated segments.

102. The apparatus of claim 101, wherein dynamically allocating the plurality of segments includes randomly allocating the segments from within a heap.

103. The apparatus of claim 101, wherein sequentially associating the allocated segments includes sequentially associating the allocated segments using pointers.

104. The apparatus of claim 101, wherein sequentially associating the allocated segments includes sequentially associating the allocated segments using time stamps.

105. The apparatus of claim 101, wherein sequentially associating the allocated segments includes sequentially associating the allocated segments using ID numbers.

106. The apparatus of claim 101, wherein sequentially associating the allocated segments includes sequentially associating the allocated segments using content addressable memory structure tags.

107. The apparatus of claim 101, wherein the instructions, when executed, further provide for sequentially allocating the respective plurality of entries in each allocated segment.

108. The apparatus of claim 101, wherein the instructions, when executed, further provide for storing sequential allocation information for the allocated segments in a data structure that is auxiliary to the non-circular data structure.

109. The apparatus of claim 101, wherein the instructions, when executed, further provide for storing sequential allocation information for the allocated segments in each of the allocated segments.

110. The method of claim 101, wherein the allocated segments are discontiguous in the data structure.

111. The apparatus of claim 101, wherein the instructions, when executed, further provide for dynamically changing a size of the plurality of segments.

112. The apparatus of claim 101, wherein allocating the segments includes allocating a single wrap bit.

113-137. -137. (canceled)