Bit Line Pre-Charge With Current Reduction

• US 20160099066A1
• Filed: 10/01/2014
• Published: 04/07/2016
• Est. Priority Date: 10/01/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dunga, Mohan Vamsi, Higashitani, Masaaki
• Granted Patent: US 9,368,222 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.

Claims

1. A method of operating a non-volatile storage device, the method comprising:

applying a pre-charge voltage to a group of bit lines that include selected bit lines associated with selected NAND strings and inhibited bit lines associated with inhibited NAND strings;

passing the pre-charge voltage to channels of the selected NAND strings and to channels of the inhibited NAND strings;

reducing the voltage on the inhibited bit lines from the pre-charge voltage to a program inhibit voltage;

reducing the voltage on the selected bit lines from the pre-charge voltage to a program enable voltage; and

discharging the pre-charge voltage from the channels of the selected NAND strings while maintaining the pre-charge voltage in the channels of the inhibited NAND strings.

2. The method of claim 1, wherein each of the NAND strings have a drain side select gate, the NAND strings are associated with a drain side select line, wherein the passing the pre-charge voltage to channels of the selected NAND strings and to channels of the inhibited NAND strings comprises:

applying a voltage to the drain side select line that turns on the drain side select gates of both the selected NAND strings and the inhibited NAND strings while the pre-charge voltage is applied to the group of bit lines.

3. The method of claim 2, wherein the discharging the pre-charge voltage from the channels of the selected NAND strings while maintaining the pre-charge voltage in the channels of the inhibited NAND strings comprises:

applying a voltage to the drain side select line that turns off the drain side select gates of the inhibited NAND strings and that turns on the drain side select gates of the selected NAND strings.

4. The method of claim 1, wherein the passing the pre-charge voltage to channels of the selected NAND strings and to channels of the inhibited NAND strings comprises:

connecting the selected NAND strings to their respective selected bit lines while connecting the inhibited NAND strings to their respective inhibited bit lines.

5. The method of claim 1, wherein the reducing the voltage on the inhibited bit lines from the pre-charge voltage to a program inhibit voltage and the reducing the voltage on the selected bit lines from the pre-charge voltage to a program enable voltage comprises:

reducing the voltage on the inhibited bit lines from the pre-charge voltage to the program inhibit voltage while reducing the voltage on the selected bit lines from the pre-charge voltage to the program enable voltage.

6. The method of claim 1, further comprising applying a boosting voltage to unselected word lines associated with the NAND strings after maintaining the pre-charge voltage in the channels of the inhibited NAND strings.

7. The method of claim 1, further comprising:

boosting voltages in the channels of the inhibited NAND strings from the pre-charge voltage to a boosted channel voltage; and

applying a programming voltage to a selected word line associated with the selected and unselected NAND strings with the channels of the inhibited NAND strings at the boosted channel voltage.

8. The method of claim 1, wherein the NAND strings are in a 3D memory array.

9. The method of claim 1, wherein the reducing the voltage on the selected bit lines from the pre-charge voltage to a program enable voltage comprises:

reducing the voltage on the selected bit lines from the pre-charge voltage to the program inhibit voltage; and

reducing the voltage on the selected bit lines from the program inhibit voltage to the program enable voltage.

10. A non-volatile storage device, comprising:

a plurality of bit lines;

a plurality of NAND strings associated with the plurality of bit lines, the NAND strings each having a channel; and

managing circuitry in communication with the plurality of bit lines and the plurality of NAND strings, the managing circuitry is configured to apply a pre-charge voltage to selected bit lines associated with selected NAND strings and inhibited bit lines associated with inhibited NAND strings, the managing circuitry is configured to pass the pre-charge voltage to the channels of the selected NAND strings and to the channels of the inhibited NAND strings, the managing circuitry is configured to reduce the voltage on the inhibited bit lines from the pre-charge voltage to a program inhibit voltage, the managing circuitry is configured to reduce the voltage on the selected bit lines from the pre-charge voltage to a program enable voltage, the managing circuitry is configured to discharge the pre-charge voltage from the channels of the selected NAND strings while maintaining the pre-charge voltage in the channels of the inhibited NAND strings.

11. The non-volatile storage device of claim 10, wherein the NAND strings each comprise a drain side select gate, and further comprising a drain side select line connected to the drain side select gates, the managing circuitry being configured to pass the pre-charge voltage to the channels of the selected NAND strings and to the channels of the inhibited NAND strings comprises the managing circuitry being configured to:

apply a voltage to the drain side select line that turns on the drain side select gates of both the selected NAND strings and the inhibited NAND strings while the pre-charge voltage is applied to the selected bit lines and the inhibited bit lines.

12. The non-volatile storage device of claim 11, wherein the managing circuitry being configured to discharge the pre-charge voltage from the channels of the selected NAND strings while maintaining the pre-charge voltage in the channels of the inhibited NAND strings comprises the managing circuitry being configured to:

apply a voltage to the drain side select line that turns off the drain side select gates of the inhibited NAND strings and that turns on the drain side select gates of the selected NAND strings.

13. The non-volatile storage device of claim 10, wherein the managing circuitry being configured to reduce the voltage on the inhibited bit lines from the pre-charge voltage to the program inhibit voltage while reducing the voltage on the selected bit lines from the pre-charge voltage to the program enable voltage comprises the managing circuitry being configured to:

reduce the voltage on the inhibited bit lines from the pre-charge voltage to the program inhibit voltage while reducing the voltage on the selected bit lines from the pre-charge voltage to the program enable voltage, wherein a voltage difference between the program inhibit voltage and the program enable voltage is less than the pre-charge voltage.

14. The non-volatile storage device of claim 10, wherein the NAND strings are in a 3D memory array.

15. The non-volatile storage device of claim 10, wherein the managing circuitry is further configured to:

boost voltages in the channels of the inhibited NAND strings from the pre-charge voltage to a boosted channel voltage and to apply a programming voltage to a selected word line associated with the selected and unselected NAND strings with the channels of the inhibited NAND strings at the boosted channel voltage.

16. The non-volatile storage device of claim 10, wherein the NAND strings comprise memory cells having charge storage trapping layers.

17. The non-volatile storage device of claim 10, wherein the managing circuitry being configured to reduce the voltage on the selected bit lines from the pre-charge voltage to a program enable voltage comprises the managing circuitry being configured to reduce the voltage on the selected bit lines from the pre-charge voltage to the program inhibit voltage while the managing circuitry lowers the voltage on the inhibited bit lines from the pre-charge voltage to the program inhibit voltage, and then reduce the voltage on the selected bit lines from the program inhibit voltage to the program enable voltage.

18. A method of operating a non-volatile storage device, the method comprising:

applying a pre-charge voltage to a group of bit lines that include selected bit lines and inhibited bit lines, the group of bit lines being associated with a group of drain side select gates, each of the bit lines being associated with a NAND string of non-volatile storage elements;

applying a voltage to a drain side select line that turns on the drain side select gates of both selected NAND strings and unselected NAND strings while the pre-charge voltage is applied to the group of bit lines;

applying a voltage to the drain side select line that turns off the drain side select gates of unselected NAND strings after applying the voltage to the drain side select line that turns on the drain side select gates of both selected NAND strings and unselected NAND strings;

applying a program inhibit voltage to the inhibited bit lines after applying the voltage to the drain side select line that turns off the drain side select gates of the unselected NAND strings;

applying a program enable voltage to the selected bit lines while applying the program inhibit voltage to the inhibited bit lines; and

applying a voltage to the drain side select line to a level that keeps off the drain side select gates associated with the inhibited bit lines while the inhibited bit lines are at the program inhibit voltage and that turns on the drain side select gates that are associated with the selected bit lines while the selected bit lines are at the program enable voltage.

19. The method of claim 18, wherein the applying a program inhibit voltage to the inhibited bit lines and the applying a program enable voltage to the selected bit lines comprise:

reducing the voltage on the inhibited bit lines from the pre-charge voltage to the inhibit voltage while reducing the voltage on the selected bit lines from the pre-charge voltage to the program enable voltage.

20. The method of claim 19, further comprising:

applying a boosting voltage to unselected word lines associated with the NAND strings while applying the program inhibit voltage to the inhibited bit lines; and

applying a programming voltage to a selected word line associated with the NAND strings while applying the program enable voltage to the selected bit lines and while applying the boosting voltage to the unselected word lines.

21. The method of claim 18, wherein the NAND strings are in a 3D memory array.

22. A 3D non-volatile storage device comprising:

a substrate;

a plurality of word lines layers;

a plurality of insulator layers alternating with the word line layers in a stack;

a plurality of strings of non-volatile storage elements formed above the substrate in a three-dimensional memory array, each of the strings having an active area comprising a channel that extends vertically through the plurality of word lines layers and the plurality of insulator layers, each string comprising a plurality of non-volatile storage elements and a drain side select gate;

a plurality of bit lines associated with the non-volatile storage element strings;

a drain side select line coupled to the drain side select gates; and

managing circuitry in communication with the plurality of bit lines, the plurality of strings, and the drain side select line, the managing circuitry applies a pre-charge voltage to selected bit lines and unselected bit lines in the plurality of bit lines, the managing circuitry applies a voltage to the drain side select line that turns on the drain side select gates while the pre-charge voltage is applied to the selected bit lines and the unselected bit lines, the managing circuitry applies a voltage to the drain side select line that turns off the drain side select gates of unselected NAND strings after applying the voltage to the drain side select line that turns on the drain side select gates of both selected NAND strings and unselected NAND strings, the managing circuitry reduces the voltage on the unselected bit lines from the pre-charge voltage to a program inhibit voltage while the managing circuitry reduces the voltage on the selected bit lines from the pre-charge voltage to a program enable voltage, the managing circuitry applies a voltage to the drain side select line to a level that keeps off the drain side select gates associated with the unselected bit lines while the unselected bit lines are at the program inhibit voltage and turns on the drain side select gates that are associated with the selected bit lines while the selected bit lines are at the program enable voltage.

23. A non-volatile storage device, comprising:

means for applying a pre-charge voltage to a group of bit lines that include selected bit lines associated with selected NAND strings and inhibited bit lines associated with inhibited NAND strings;

means for passing the pre-charge voltage to channels of the selected NAND strings and to channels of the inhibited NAND strings;

means for reducing the voltage on the inhibited bit lines from the pre-charge voltage to a program inhibit voltage;

means for reducing the voltage on the selected bit lines from the pre-charge voltage to a program enable voltage; and

means for discharging the pre-charge voltage from the channels of the selected NAND strings while maintaining the pre-charge voltage in the channels of the inhibited NAND strings.