Method for Manufacturing a Semiconductor Switching Device with Different Local Cell Geometry

• US 20160099180A1
• Filed: 12/14/2015
• Published: 04/07/2016
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Fachmann, Christian, Vecino Vazquez, Enrique
• Granted Patent: US 9,583,395 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim, and forming a plurality of switchable cells in the active area. Each of the switchable cells includes a body region, a gate electrode structure, and a source region. The active area defined by the switchable cells includes at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region. The method further includes forming a source metallization in ohmic contact with the source regions of the switchable cells, and forming a gate metallization in ohmic contact with the gate electrode structures of the switchable cells.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate comprising an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim;

forming a plurality of switchable cells in the active area, wherein each of the switchable cells comprises a body region, a gate electrode structure, and a source region, wherein the active area defined by the switchable cells comprises at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region;

forming a source metallization in ohmic contact with the source regions of the switchable cells; and

forming a gate metallization in ohmic contact with the gate electrode structures of the switchable cells.

2. The method of claim 1, further comprising:

providing the switchable cells in the first switchable region with a first specific coverage ratio defined by a ratio of the area of the gate electrode structure of said switchable cell to the total area of said switchable cell; and

providing the switchable cells in the second switchable region with a second specific coverage ratio defined by a ratio of the area of the gate electrode structure of said switchable cell to the total area of said switchable cell, wherein the first specific coverage ratio of switchable cells in the first switchable region is different to the second specific coverage ratio of switchable cells in the second switchable region.

3. The method of claim 1, further comprising:

disposing the switchable cells in the first switchable region at a first longitudinal pitch; and

disposing the switchable cells in the second switchable region at a second longitudinal pitch, wherein the first longitudinal pitch of the switchable cells in the first switchable region is different to the second longitudinal pitch of the second switchable cells in the second switchable region.