MULTI-CHIP PACKAGE, TEST SYSTEM AND METHOD OF OPERATING THE SAME

• US 20160099230A1
• Filed: 03/19/2015
• Published: 04/07/2016
• Est. Priority Date: 10/01/2014
• Status: Abandoned Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KANG, Yong-Gu, CHO, Ho-Sung
• Application Number:
  US14/663,112
• Publication Number:
  US 20160099230A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multi-chip package includes: a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias; a state detection device suitable for detecting connection states of the normal through silicon vias and the repair through silicon vias; and a repair control device suitable for comparing the connection state of the normal through silicon vias with the connection state of the repair through silicon vias, and controlling whether to perform a repair operation.

Claims

1. A multi-chip package comprising:

a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias;

a state detection device suitable for detecting connection states of the normal through silicon vias and the repair through silicon vias; and

a repair control device suitable for comparing the connection states of the normal through silicon vias with the connection states of the repair through silicon vias, and controlling whether to perform a repair operation.

2. The multi-chip package of claim 1, wherein test data is applied to each of the normal through silicon vias and the repair through silicon vias during a test operation.

3. The multi-chip package of claim 1, wherein the state detection device includes:

a first normal/failed detector suitable for receiving test data transmitted through the normal through silicon vias and generating a first detection signal; and

a second normal/failed detector suitable for receiving test data transmitted through the repair through silicon vias and generating a second detection signal.

4. The multi-chip package of claim 1, wherein the repair control device includes:

a normal/failed counter suitable for receiving an output signal of the state detection device and counting a number of normal through silicon vias that are failed and a number of repair through silicon vias that operate normally;

an enable controller suitable for comparing the number of normal through silicon vias that are failed with the number of repair through silicon vias that operate normally, and generating an enable control signal; and

a control signal generator enabled in response to the enable control signal, suitable for generating a repair control signal for controlling repair operations of the normal through silicon vias and the repair through silicon vias.

5. A method of operating a multi-chip package including a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias, the method comprising:

applying a test data to each of the normal through silicon vias and the repair through silicon vias;

determining a number of normal through silicon vias that are failed, a number of normal through silicon vias that operate normally, a number of repair through silicon vias that are failed, and a number of repair through silicon vias that operate normally based on the test data;

deciding whether to perform a repair operation based on the number of normal through silicon vias that are failed, the number of normal through silicon vias that operate normally, the number of repair through silicon vias that are failed, and the number of repair through silicon vias that operate normally to produce a decision result; and

performing the repair operation based on the decision result.

6. The method of claim 5, wherein, in the deciding of whether to perform the repair operation,

the number of normal through silicon vias that are failed is compared with the number of repair through silicon vias that operate normally.

7. The method of claim 5, further comprising:

detecting a time taken for performing the repair operation based on the number of normal through silicon vias that are failed, the number of normal through silicon vias that operate normally, the number of repair through silicon vias that are failed, and the number of repair through silicon vias that operate normally.

8. A test system comprising:

a multi-chip package which includes;

a plurality of semiconductor chips that are coupled with each other through normal through silicon vias and repair through silicon vias,

a state detection device suitable for detecting connection states of the normal through silicon vias and the repair through silicon vias, and

a repair control device suitable for comparing the connection states of the normal through silicon vias with the connection states of the repair through silicon vias, and controlling whether to perform a repair operation; and

a test device suitable for receiving the connection states of the normal through silicon vias and the repair through silicon vias and controlling when a test operation is performed on the multi-chip package.

9. The test system of claim 8, wherein the test device includes:

a normal/failed counter suitable for receiving the connection states of the normal through silicon vias and the connection states of the repair through silicon vias, and counting the number of normal through silicon vias that are failed and the number of repair through silicon vias that operate normally;

a repair time calculator suitable for calculating a number of target through silicon vias to be repaired based on an output signal of the normal/failed counter; and

a command generator suitable for generating a command signal for controlling an operation of the multi-chip package based on the number of target through silicon vias to be repaired.

10. The test system of claim 9, wherein the command signal corresponds to at least one operation of the multi-chip package, and

timing of when the command signal is enabled is controlled based on the number of target through silicon vias to be repaired.