FETS AND METHODS OF FORMING FETS

• US 20160099352A1
• Filed: 10/03/2014
• Published: 04/07/2016
• Est. Priority Date: 10/03/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Tung Ying, Huang, Yu-Lien, Lin, You-Ru
• Granted Patent: US 9,583,598 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

An embodiment is a structure. The structure comprises a fin on a substrate, isolation regions on the substrate, a dielectric region, and a gate structure. The fin includes a first epitaxial portion. The isolation regions are on opposing sides of the fin, and at least the first epitaxial portion of the fin protrudes from between the isolation regions. The dielectric region directly underlies the first epitaxial portion. A material of the dielectric region is different from a material of the isolation regions. The gate structure is along sidewalls and is over an upper surface of the fin. The gate structure defines a channel region in the first epitaxial portion.

Claims

1. A structure comprising:

a fin on a substrate, the fin comprising a first epitaxial portion;

isolation regions in the substrate and on opposing sides of the fin, at least the first epitaxial portion of the fin protruding from between the isolation regions;

a dielectric region directly underlying the first epitaxial portion, a material of the dielectric region being different from a material of the isolation regions; and

a gate structure along sidewalls and over an upper surface of the fin, the gate structure defining a channel region in the first epitaxial portion.

2. The structure of claim 1, wherein the fin further comprises a second epitaxial portion directly underlying the first epitaxial portion, the material of the dielectric region comprising an insulating derivative of a material of the second epitaxial portion.

3. The structure of claim 2, wherein the second epitaxial portion continuously connects the first epitaxial portion to a crystalline material of the substrate.

4. The structure of claim 2, wherein the second epitaxial portion is discontinuous between the first epitaxial portion and a crystalline material of the substrate.

5. The structure of claim 2, wherein a material of the first epitaxial portion is silicon, the material of the second epitaxial portion is silicon germanium, and the material of the dielectric region is silicon germanium oxide.

6. The structure of claim 1, wherein the fin further comprises a template epitaxial portion disposed between the first epitaxial portion and the dielectric region.

7. The structure of claim 1, wherein upper surfaces of the isolation regions are above an upper surface of the dielectric region.

8. The structure of claim 1, wherein the fin further comprises source/drain regions on opposing sides of the gate structure, the channel region being disposed between the source/drain regions.

9. A structure comprising:

a channel region comprising a first crystalline semiconductor material;

an intermediate region directly underlying the channel region, the intermediate region comprising a second crystalline semiconductor material and a dielectric material, the dielectric material being a derivative of the second crystalline semiconductor material;

a gate structure over the channel region; and

source/drain regions on opposing sides of the channel region.

10. The structure of claim 9, wherein the first crystalline semiconductor material is different from the second crystalline semiconductor material.

11. The structure of claim 9, wherein the second crystalline semiconductor material is continuous from an upper surface of the intermediate region to a bottom surface of the intermediate region.

12. The structure of claim 9, wherein the second crystalline semiconductor material is discontinuous from an upper surface of the intermediate region to a bottom surface of the intermediate region.

13. The structure of claim 9 further comprising a template region disposed between the channel region and the intermediate region.

14. The structure of claim 9, wherein the first crystalline semiconductor material is silicon, the second crystalline semiconductor material is silicon germanium, and the dielectric material is silicon germanium oxide.

15-20. -20. (canceled)

21. A semiconductor structure comprising:

a substrate with a first region and a second region;

an N-type device in the first region, the N-type device comprising;

a first semiconductor fin over the substrate and between isolation regions in the first region;

a first upper epitaxial portion over the first semiconductor fin, the first upper epitaxial portion comprising a first material and protruding above the isolation regions in the first region;

a first lower epitaxial portion between the first upper epitaxial portion and the first semiconductor fin, the first lower epitaxial portion comprising a second material different from the first material; and

a dielectric material around the first lower epitaxial portion; and

a P-type device in the second region, the P-type device comprising;

a second semiconductor fin over the substrate and between isolation regions in the second region;

a second upper epitaxial portion over the second semiconductor fin, the second upper epitaxial portion comprising a third material different from the first material and protruding above the isolation regions in the second region;

a second lower epitaxial portion between the second upper epitaxial portion and the second semiconductor fin, the second lower epitaxial portion comprising the second material; and

the dielectric material around the second lower epitaxial portion.

22. The semiconductor structure of claim 21, wherein the P-type device further comprises a template layer between the second upper epitaxial portion and the second lower epitaxial portion, wherein the template layer comprises the first material.

23. The semiconductor structure of claim 21, wherein the first lower epitaxial portion has a width smaller than a width of the first upper epitaxial portion.

24. The semiconductor structure of claim 23, wherein the second lower epitaxial portion has a width smaller than a width of the second upper epitaxial portion.

25. The semiconductor structure of claim 21, wherein the dielectric material is an oxide of the second material.

26. The semiconductor structure of claim 21, wherein the first material is silicon, the second material is silicon germanium, and the dielectric material is silicon germanium oxide.