BACK SIDE ILLUMINATED IMAGE SENSOR WITH GUARD RING REGION REFLECTING STRUCTURE

• US 20160099371A1
• Filed: 10/03/2014
• Published: 04/07/2016
• Est. Priority Date: 10/03/2014
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Webster, Eric A. G.
• Granted Patent: US 9,685,576 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/1465 of the hybrid type
• CPC Class Codes: H01L 31/02027 for devices working in avalanche mode
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/1075 in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
• CPC Class Codes: H04N 23/11 for generating image signals from visible and infrared light wavelengths
• CPC Class Codes: H04N 25/131 including elements passing infrared wavelengths
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

A photon detector includes a single photon avalanche diode (SPAD) disposed proximate to a front side of a semiconductor layer. The SPAD includes a multiplication junction that is reversed biased above a breakdown voltage such that light directed into the SPAD through a backside of the semiconductor layer triggers an avalanche multiplication process. A guard ring is disposed in a guard ring region that surrounds the SPAD to isolate the SPAD in the semiconductor layer. A guard ring region reflecting structure is disposed in the guard ring region proximate to the guard ring and proximate to the front side of the semiconductor layer such that light directed into the guard ring region through the backside of the semiconductor layer that bypasses the SPAD is redirected by the guard ring region reflecting structure back into the semiconductor layer and into the SPAD.

Claims

1. A photon detector, comprising:

a single photon avalanche diode (SPAD) disposed proximate to a front side of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first semiconductor layer, wherein the multiplication junction is reversed biased above a breakdown voltage such that light directed into the SPAD through a backside of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction;

a guard ring disposed in a guard ring region in the first semiconductor layer proximate to the SPAD, wherein the guard ring surrounds the SPAD to isolate the SPAD in the first semiconductor layer; and

a guard ring region reflecting structure disposed in the guard ring region proximate to the guard ring and proximate to the front side of the first semiconductor layer such that light directed into the guard ring region through the backside of the first semiconductor layer that bypasses the SPAD is redirected by the guard ring region reflecting structure back into the first semiconductor layer and into the SPAD.

2. The photon detector of claim 1 further comprising a SPAD region reflecting structure disposed proximate to the SPAD and proximate to the front side of the first semiconductor layer such that light directed into the first semiconductor layer through the backside of the first semiconductor layer that passes through the SPAD is reflected by the SPAD region reflecting structure back into the first semiconductor layer and into the SPAD.

3. The photon detector of claim 2 wherein the guard ring region reflecting structure comprises a plurality of metal layers disposed in an oxide material disposed proximate to the front side of the first semiconductor layer.

4. The photon detector of claim 3 wherein the SPAD region reflecting structure is included in one of the plurality of metal layers disposed in the oxide material disposed proximate to the front side of the first semiconductor layer.

5. The photon detector of claim 4 wherein the guard ring region reflecting structure is non-coplanar with the SPAD region reflecting structure.

6. The photon detector of claim 4 wherein the plurality of metal layers of the guard ring region reflecting structure are arranged in a flat-topped pyramid shape in the oxide material disposed proximate to the front side of the first semiconductor layer.

7. The photon detector of claim 4 wherein the guard ring region reflecting structure is included in a first, a second, and a third one of the plurality of metal layers, and wherein the SPAD region reflecting structure is included in a fourth one of the plurality of metal layers.

8. The photon detector of claim 1 wherein the first semiconductor layer includes thinned silicon.

9. The photon detector of claim 1 wherein the light includes near infrared light.

10. The photon detector of claim 1 wherein the first semiconductor layer is included in a first semiconductor device wafer, wherein the first semiconductor device wafer is stacked with a second semiconductor device wafer including readout circuitry, and wherein the first and second semiconductor device wafer are coupled together in a stacked chip system.

11. An imaging sensor system, comprising:

a pixel array having a plurality of pixel cells disposed in a first semiconductor layer, wherein each one of the plurality of pixel cells includes;

a single photon avalanche diode (SPAD) disposed proximate to a front side of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first semiconductor layer, wherein the multiplication junction is reversed biased above a breakdown voltage such that light directed into the SPAD through a backside of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction;

a guard ring disposed in a guard ring region in the first semiconductor layer proximate to the SPAD, wherein the guard ring surrounds the SPAD to isolate the SPAD in the first semiconductor layer; and

a guard ring region reflecting structure disposed in the guard ring region proximate to the guard ring and proximate to the front side of the first semiconductor layer such that light directed into the guard ring region through the backside of the first semiconductor layer that bypasses the SPAD is redirected by the guard ring region reflecting structure back into the first semiconductor layer and into the SPAD;

control circuitry coupled to the pixel array to control operation of the pixel array; and

readout circuitry coupled to the pixel array to readout image data from the plurality of pixel cells.

12. The imaging sensor system of claim 11 further comprising function logic coupled to the readout circuitry to store image data readout from the plurality of pixel cells.

13. The imaging sensor system of claim 11 wherein the readout circuitry comprises a plurality of counter circuits electrically coupled to the pixel array, wherein each one of the plurality of counter circuits is coupled to count output pulses generated by a respective one of the plurality of pixel cells.

14. The imaging sensor system of claim 13 wherein the first semiconductor layer is included in a first semiconductor device wafer, and wherein the readout circuitry is included in a second semiconductor layer included in a second semiconductor device wafer, wherein the first semiconductor device wafer is stacked with and coupled to the second semiconductor device wafer in a stacked chip system.

15. The imaging sensor system of claim 11 wherein each one of the plurality of pixel cells further comprising a SPAD region reflecting structure disposed proximate to the SPAD and proximate to the front side of the first semiconductor layer such that light directed into the first semiconductor layer through the backside of the first semiconductor layer that passes through the SPAD is reflected by the SPAD region reflecting structure back into the first semiconductor layer and into the SPAD.

16. The imaging sensor system of claim 15 wherein the guard ring region reflecting structure is included in a plurality of metal layers disposed in an oxide material disposed proximate to the front side of the first semiconductor layer.

17. The imaging sensor system of claim 16 wherein the SPAD region reflecting structure is included in one of the plurality of metal layers disposed in the oxide material disposed proximate to the front side of the first semiconductor layer.

18. The imaging sensor system of claim 17 wherein the guard ring region reflecting structure is non-coplanar with the SPAD region reflecting structure.

19. The imaging sensor system of claim 17 wherein the plurality of metal layers of the guard ring region reflecting structure are arranged in a flat-topped pyramid shape in the oxide material disposed proximate to the front side of the first semiconductor layer.

20. The imaging sensor system of claim 17 wherein the guard ring region reflecting structure is included in a first, a second, and a third one of the plurality of metal layers, and wherein the SPAD region reflecting structure is included in a fourth one of the plurality of metal layers.

21. The imaging sensor system of claim 11 wherein the first semiconductor layer includes thinned silicon.

22. The imaging sensor system of claim 11 wherein the light includes near infrared light.