ESTIMATION CIRCUIT FOR SOC AND SOH OF BATTERY

• US 20160103181A1
• Filed: 11/21/2014
• Published: 04/14/2016
• Est. Priority Date: 10/14/2014
• Status: Active Grant

• Current Assignee: National Sun Yat-sen University
• Original Assignee: National Sun Yat-sen University
• Inventors: Wang, Chua-Chin, Lu, Wen-Je, Tseng, Min-Yu
• Granted Patent: US 9,817,076 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/367 Software therefor, e.g. for battery testing using modelling or look-up tables
• CPC Class Codes: G01R 31/3828 using current integration
• CPC Class Codes: G01R 31/392 Determining battery ageing or deterioration, e.g. state of health

Abstract

Estimation circuit for SOC and SOH of battery includes a control circuit, a current estimation circuit, an open-circuit voltage detection circuit, an optional multiplexer and an electrical-capacity calculation circuit. The control circuit operates under six modes based on a reset signal, a voltage signal and a current signal. The current estimation circuit comprises a current modification circuit and a Coulomb integral circuit, the current modification circuit receives the current signal and outputs a modifying current signal, the Coulomb integral circuit integrates the modifying current signal to obtain an estimating electrical-capacity value. The open-circuit voltage detection circuit receives the voltage signal and outputs an initial electrical-capacity value. The optional multiplexer receives an estimation optional signal, the estimating electrical-capacity value and the initial electrical-capacity value to output an estimating electrical-capacity signal. The electrical-capacity calculation circuit stores the estimating electrical-capacity signal to calculate battery-electrical-capacity remaining signal and state of health signal.

Claims

1. An estimation circuit for SOC and SOH of battery includes:

a control circuit for receiving a reset signal, a voltage signal and a current signal, the control circuit determines the voltage level of an electrical-capacity calculation reset signal, an estimation optional signal, an over voltage enable signal, a normal state enable signal, a low voltage enable signal and a current-estimated reset signal outputted from the control circuit according to the reset signal, the voltage signal and the current signal;

a current estimation circuit having a current modification circuit and a Coulomb integral circuit, wherein the current modification circuit receives the current signal and multiplies the current signal by a modification parameter and outputs a modified current signal, the Coulomb integral circuit receives the modified current signal and the current-estimated reset signal of the control signal and integrates the modified current signal for outputting an estimating electrical-capacity value;

an open-circuit voltage detection circuit for receiving the voltage signal, wherein the open-circuit voltage detection circuit outputs an initial electrical-capacity value via the voltage signal;

an optional multiplexer for receiving the estimation optional signal of the control circuit, the estimating electrical-capacity value of the current estimation circuit and the initial electrical-capacity value of the open-circuit voltage detection circuit, the optional multiplexer outputs an estimating electrical-capacity signal and determines the estimating electrical-capacity signal equal to the estimating electrical-capacity value or the initial electrical-capacity value according to the estimation optional signal; and

an electrical-capacity calculation circuit having an over voltage register, a normal state register and a low voltage register, wherein the over voltage register receives the estimating electrical-capacity signal, the electrical-capacity calculation reset signal and the over voltage enable signal, the normal state register receives the estimating electrical-capacity signal, the electrical-capacity calculation reset signal and the normal state enable signal, the low voltage register receives the estimating electrical-capacity signal, the electrical-capacity calculation reset signal and the low voltage enable signal, wherein the over voltage register, the normal state register and the low voltage register determine whether to store the estimating electrical-capacity signal is controlled by the over voltage enable signal, the normal state enable signal and the low voltage enable signal respectively, wherein the difference value between a signal stored in the normal state register and a signal stored in the low voltage register is a battery electrical-capacity remaining signal, and the difference value between a signal stored in the over voltage register and the signal stored in the low voltage register is a battery state of health signal.

2. The estimation circuit in accordance with claim 1, wherein the current modification circuit comprises a current decoder, a comparison table, a first multiplexer and a first multiplier, the current decoder receives the current signal and decodes the current signal to generate a symbol bit and a current decoding signal, the first multiplexer receives the current decoding signal and outputs the modifying parameter on the basis of the current decoding signal and the comparison table, the first multiplier multiplies the current decoding signal with the modifying parameter to obtain the modified current signal.

3. The estimation circuit in accordance with claim 2, wherein the Coulomb integral circuit comprises a first register, a second register, a second multiplier, a first adder and a third register, the first register receives the symbol bit of the current decoder and a first pulse signal, the second register receives the modified current signal and the first pulse signal to store the modified current signal, the second multiplier receives the modified current signal stored in the second register and a sampling time and multiplies the modified current signal with the sampling time to obtain a product signal, the first adder adds a former estimated electrical-capacity value to the product signal to obtain the estimating electrical-capacity value, the third register receives the estimating electrical-capacity value and the first pulse signal for storing the estimating electrical-capacity value, and the third register outputs the former estimated electrical-capacity value.

4. The estimation circuit in accordance with claim 3, wherein the over voltage register, the normal state register and the low voltage register receive a second pulse signal to make the over voltage register, the normal state register and the low voltage register storing the estimating electrical-capacity signal via trigger of the second pulse signal.

5. The estimation circuit in accordance with claim 4 further includes a frequency divider for outputting the first pulse signal and the second pulse signal, wherein the frequency of the first pulse signal is less than that of the second pulse signal.

6. The estimation circuit in accordance with claim 1, wherein the open-circuit voltage detection circuit comprises a first operation unit, a second operation unit, a third operation unit, a comparator, a second multiplexer, a third multiplier and a second adder, the first operation unit receives the voltage signal for calculating a first battery capacity state, the second operation unit receives the voltage signal for calculating a second battery capacity state, the third operation unit receives the voltage signal for calculating a third battery capacity state, the second multiplexer receives the first battery capacity state, the second battery capacity state, and the third battery capacity state, the comparator receives the voltage signal and controls the second multiplexer to output the first battery capacity state, the second battery capacity state or the third battery capacity state to the third multiplier via the voltage signal, the third multiplier multiplies received signal with a total battery capacity value and adds the signal stored in the low voltage register via the second adder for obtaining the initial electrical-capacity value.

7. The estimation circuit in accordance with claim 1, wherein when the control circuit enters into a reset mode via the reset signal, the electrical-capacity calculation reset signal and the current-estimated reset signal are high voltage level for resetting the current estimation circuit and the electrical-capacity calculation circuit.

8. The estimation circuit in accordance with claim 1, wherein when the current signal received by the control circuit is smaller than a pre-determined value and the voltage signal is not able to maintain stabilization in a pre-determined time, the control circuit enters an OCV buffer mode, wherein the electrical-capacity calculation reset signal, the over voltage enable signal, the normal state enable signal and the low voltage enable signal are low voltage level for shutting down the over voltage register, the normal state register and the low voltage register.

9. The estimation circuit in accordance with claim 1, wherein when the current signal received by the control circuit is smaller than a pre-determined value and the voltage signal maintains stabilization in a pre-determined time, the control circuit enters an OCV mode, wherein the estimation optional signal outputted from the control circuit enables the estimating electrical-capacity signal outputted from the optional multiplexer equal to the initial electrical-capacity value, and the normal state enable signal is changed to high voltage level for making the estimating electrical-capacity signal stored in the normal state register.

10. The estimation circuit in accordance with claim 1, wherein when the voltage signal received by the control circuit is larger than a charging cut-off voltage, the control circuit enters an over voltage mode, wherein the estimation optional signal outputted from the control circuit enables the estimating electrical-capacity signal outputted from the optional multiplexer equal to the estimating electrical-capacity value, and the over voltage enable signal and the normal state enable signal change to high voltage level for making the estimating electrical-capacity signal stored in the over voltage register and the normal state register.

11. The estimation circuit in accordance with claim 1, wherein when the voltage signal received by the control circuit is smaller than a discharge cut-off voltage, the control circuit enters a under voltage mode, wherein the estimation optional signal outputted from the control circuit enables the estimating electrical-capacity signal outputted from the optional multiplexer equal to the estimating electrical-capacity value, and the low voltage enable signal and the normal state enable signal change to high voltage level for making the estimating electrical-capacity signal stored in the low voltage register and the normal state register.

12. The estimation circuit in accordance with claim 1, wherein when the voltage signal received by the control circuit is not less than a discharge cut-off voltage and not larger than a charge cut-off voltage, the control circuit enters a normal mode, wherein the estimation optional signal outputted from the control circuit enables estimating electrical-capacity signal outputted from the optional multiplexer equal to the estimating electrical-capacity value, and the normal state enable signal changes to high voltage level for making the estimating electrical-capacity signal stored in the normal state register.

13. The estimation circuit in accordance with claim 1, wherein the formula of the modification parameter is: