INTEGRATED FLOATING DIODE STRUCTURE AND METHOD THEREFOR

• US 20160104781A1
• Filed: 10/13/2014
• Published: 04/14/2016
• Est. Priority Date: 10/13/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Janssens, Johan Camiel Julia, Pjencak, Jaroslav
• Granted Patent: US 9,425,266 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/6609 Diodes
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a floating diode structure includes a p-type semiconductor substrate. An n-type doped region is disposed between the semiconductor substrate and a p-type doped region of the first conductivity type adjacent the first doped region. An n-type cathode region is disposed within the p-type doped region and a p-type anode region is disposed within the cathode region. An anode electrode is connected to the anode region and a cathode electrode is connected to the cathode region. In one embodiment, the cathode electrode is further connected to the p-type doped region. The n-type doped region is configured as a floating region that facilitates the diode operating in both a forward and reverse bias mode and both below ground and above ground with respect to the p-type semiconductor substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a first doped region of a second conductivity type opposite to the first conductivity type on the semiconductor substrate;

a second doped region of the first conductivity type adjacent the first doped region;

a cathode region of the second conductivity type within the second doped region;

an anode region of the first conductivity type within the cathode region;

a first electrode electrically coupled to the anode region; and

a second electrode electrically coupled to the cathode region and the second doped region, wherein first doped region is configured as a floating region.

2. The semiconductor device of claim 1, wherein the first doped region comprises:

a first portion adjacent the substrate and having a first doping concentration; and

a second portion adjacent the first portion and the second doped region, wherein the second portion has a second doping concentration, and wherein the second doping concentration is greater than the first doping concentration, and wherein the second doping concentration is selected to reduce current injection into the semiconductor substrate.

3. The semiconductor device of claim 2, wherein the second doping concentration is greater than about 1.0×

10²⁰ atoms/cm³.

4. The semiconductor device of claim 2, wherein the first doped region further comprises sinker portions that laterally surround the second doped region.

5. The semiconductor device of claim 1, wherein the first doped region is configured to be self-biased by one or more of the second doped region and the semiconductor substrate.

6. The semiconductor device of claim 1, wherein the anode region comprises a pair of stripe regions.

7. The semiconductor device of claim 6 further comprising a third doped region of the first conductivity type within the second doped region, wherein a portion of the third doped region extends between the pair of stripe regions.

8. The semiconductor device of claim 7 further comprising:

a fourth doped region of the second conductivity type within a portion of the cathode region and laterally surrounding one of the pair of stripes;

a fifth doped region of the second conductivity type within the another portion of the cathode region and laterally surrounding another one of the pair of stripes, wherein the fourth doped region and fifth doped region are electrically coupled to the second electrode.

9. The semiconductor device of claim 7, wherein the third doped region is electrically coupled to the second electrode.

10. The semiconductor device of claim 1, wherein the cathode region is disposed apart from edge portions of the second doped region, and wherein the second doped region is electrically coupled to the second electrode between an edge portion and the second doped region.

11. A semiconductor diode structure comprising:

a semiconductor substrate of a first conductivity type;

a first doped region of a second conductivity type opposite to the first conductivity type, the first doped region having a first portion adjacent the semiconductor substrate and having a first doping concentration and a second portion adjacent the first portion and having a second doping concentration greater than the first doping concentration;

a second doped region of the first conductivity type adjacent the second portion of the first doped region;

a cathode region of the second conductivity type within the second doped region;

an anode region of the first conductivity type within the cathode region, wherein the cathode region and anode region form the semiconductor diode;

a first electrode electrically coupled to the anode region; and

a second electrode electrically coupled to the cathode region, wherein the first doped region is configured to operate absent a low-ohmic external voltage imposed on the first doped region, and wherein the second doping concentration is selected to reduce current injection from the semiconductor diode into the semiconductor substrate.

12. The structure of claim 11, wherein second doped region is electrically coupled to the second electrode.

13. The structure of claim 11, wherein the second doping concentration within at least a part of the second portion is greater than about 1.0×

10²⁰ atoms/cm³.

14. The structure of claim 11, wherein the first doped region further comprises sinker portions that laterally surround the second doped region.

15. The structure of claim 11, wherein the anode region comprises a pair of stripe regions, the structure further comprising:

a third doped region of the first conductivity type within the second doped region, wherein a portion of the third doped region extends between the pair of stripe regions.

16. A method of forming a semiconductor device comprising:

providing a semiconductor substrate of a first conductivity type, a first doped region of a second conductivity type opposite to the first conductivity type on the semiconductor substrate, and a second doped region of the first conductivity type adjacent the first doped region;

forming a cathode region of the second conductivity type within the second doped region;

forming an anode region of the first conductivity type within the cathode region;

forming a first electrode coupled to the anode region; and

forming a second electrode coupled to the cathode region and the second doped region, wherein first doped region is configured as a floating region.

17. The method of claim 16, wherein providing the first doped region comprises:

providing a first portion adjacent the substrate and having a first doping concentration; and

providing a second portion adjacent the first portion and the second doped region having a second doping concentration, wherein the second doping concentration is greater than the first doping concentration, and wherein the second doping concentration is selected to reduce current injection into the semiconductor substrate.

18. The method of claim 17, wherein providing the second portion includes providing the second doping concentration greater than about 1.0×

10²⁰ atoms/cm³.

19. The method of claim 16, further comprising forming sinker portions of the second conductivity type laterally surround the second doped region.

20. The method of claim 16, wherein forming the anode region comprises forming anode region including a pair of stripe regions, and wherein the method further comprises forming a third doped region of the first conductivity type within the second doped region, wherein a portion of the third doped region extends between the pair of stripe regions.