SEMICONDUCTOR DEVICE

• US 20160105188A1
• Filed: 08/27/2015
• Published: 04/14/2016
• Est. Priority Date: 10/10/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jong-Pil Cho, Young-Joo Lee
• Inventors: CHO, JONG-PIL, LEE, YOUNG-JOO
• Granted Patent: US 9,634,674 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04B 5/70 specially adapted for specific purposes
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04B 5/77 for interrogation
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader.

Claims

1. A semiconductor device comprising:

an antenna that receives a first clock from a reader;

a phase locked loop (PLL) that receives the received first clock and provides m candidate clocks having different phases derived from the first clock, where ‘

m’

is a natural number;

a phase difference detector that receives the first clock and a selected clock selected from among the m candidate clocks, and detect a phase difference between the first clock and the selected clock;

a phase difference controller that receives the detected phase difference from the phase difference detector and selects another selected clock from among the m candidate clocks; and

a driver that receives the another selected clock from the phase difference controller and transmission data to be output to the reader, and provides the transmission data synchronously with the another selected clock to the reader.

2. The semiconductor device of claim 1, wherein the PLL includes a voltage controlled oscillator (VCO) that provides the m candidate clocks.

3. The semiconductor device of claim 1, further comprising:

a multiplexer that provides the selected clock in response to a received initial value, and provides the another selected clock in response to an output of the phase difference controller.

4. The semiconductor device of claim 3, further comprising:

a memory that stores the predetermined phase difference, wherein the another selected clock is a clock among the m candidate clocks having a phase difference relative to the first clock closest to the predetermined phase difference.

5. The semiconductor device of claim 4, further comprising:

a variable delay line that receives the another selected clock and performs fine tuning to adjust a phase difference between the another selected clock and the first clock approach to the predetermined phase difference.

6. The semiconductor device of claim 1, wherein the phase difference controller selects the another selected clock from among the m candidate clocks in response to a first time period during which the first clock is received from the reader and a second time period during which an output of the driver is provided to the reader.

7. The semiconductor device of claim 1, wherein the semiconductor device is configured as a near field communication (NFC) card.

8. The semiconductor device of claim 1, further comprising:

a field level detector that detects a level of a field generated between the reader and the antenna, wherein the phase difference controller selects the another selected clock from among the m candidate clocks in response to an output of the field level detector.

9. The semiconductor device of claim 8, further comprising:

a memory that stores a predetermined phase difference, wherein the predetermined phase difference is determined in response to the output of the field level detector.

10. The semiconductor device of claim 9, wherein the predetermined phase difference is reduced as the level of the field generated between the reader and the antenna increases.

11. A semiconductor device comprising:

an antenna that receives a first clock from a reader;

a phase locked loop (PLL) that receives the first clock and outputs a second clock having a predetermined phase difference with the first clock;

a driver that receives the second clock output and transmission data to be output to the reader, and outputs the transmission data to the reader synchronously with the second clock; and

an output controller that varies a magnitude of an output signal of the driver.

12. The semiconductor device of claim 11, wherein the output controller comprises:

a field level detector that detects a level of a field generated between the reader and the antenna; and

a driver controller that controls the magnitude of the output signal of the driver in response to an output of the field level detector.

13. The semiconductor device of claim 12, wherein the output controller includes a discharger enabled when a level of the transmission data is low and controlling the magnitude of the output signal of the driver.

14. The semiconductor device of claim 13, wherein the discharger comprises:

a first discharger connected to a first signal path that communicates the first clock from the antenna to the PLL; and

a second discharger connected to a second signal path that communicates the transmission data synchronously with the second clock from the driver to the antenna.

15. The semiconductor device of claim 14, wherein the discharger is disabled in a modulation low period in which the transmission data is not provided to the driver and is enabled when the transmission data is at a low level in a modulation high period in which the transmission data is provided to the driver.

16. A semiconductor device comprising:

an antenna configured that receives a first clock from a reader;

a phase locked loop (PLL) that receives the first clock and provides a second clock having a predetermined phase difference with the first clock;

a driver that receives the second clock and transmission data to be output to the reader, and outputs the transmission data to the reader synchronously with the second clock; and

a duty ratio controller that varies a duty ratio of the transmission data synchronously provided to the driver.

17. The semiconductor device of claim 16, wherein the duty ratio controller comprises:

a field level detector that detects a level of a field generated between the reader and the antenna; and

a controller that controls the duty ratio of the transmission data synchronously provided to the reader in response an output of the field level detector.

18. The semiconductor device of claim 17, wherein the controller decreases a duty ratio during a time period in which the transmission data is at a high level, and increases the duty ratio during a time period in which the transmission data is at a low level.

19. The semiconductor device of claim 17, wherein the controller increases a duty ratio during a time period in which the transmission data is at a high level, and decreases the duty ratio during a time period in which the transmission data is at a low level.

20. The semiconductor device of claim 16, wherein the semiconductor device is configured as a near field communication (NFC) card.