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SEMICONDUCTOR DEVICE

  • US 20160105188A1
  • Filed: 08/27/2015
  • Published: 04/14/2016
  • Est. Priority Date: 10/10/2014
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • an antenna that receives a first clock from a reader;

    a phase locked loop (PLL) that receives the received first clock and provides m candidate clocks having different phases derived from the first clock, where ‘

    m’

    is a natural number;

    a phase difference detector that receives the first clock and a selected clock selected from among the m candidate clocks, and detect a phase difference between the first clock and the selected clock;

    a phase difference controller that receives the detected phase difference from the phase difference detector and selects another selected clock from among the m candidate clocks; and

    a driver that receives the another selected clock from the phase difference controller and transmission data to be output to the reader, and provides the transmission data synchronously with the another selected clock to the reader.

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