HYBRID MEMORY MODULE STRUCTURE AND METHOD OF DRIVING THE SAME

• US 20160110102A1
• Filed: 06/15/2015
• Published: 04/21/2016
• Est. Priority Date: 10/20/2014
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Sang-Kil
• Application Number:
  US14/740,221
• Publication Number:
  US 20160110102A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A hybrid memory module structure includes a channel for receiving data from and transmitting data to a device external to the hybrid memory module structure, a first memory module connected to the channel, and a second memory module connected to the channel. The first memory module includes at least a first memory and a second memory, the first memory being a working memory and the second memory being a storage memory. The second memory module includes at least a third memory and a fourth memory, the third memory being a working memory and the fourth memory being a storage memory. The channel includes a first data line commonly connected to the first memory and the second memory, and a second data line commonly connected to the third memory and the fourth memory.

Claims

1. A hybrid memory module structure comprising:

a channel for receiving data from and transmitting data to a device external to the hybrid memory module structure;

a first memory module connected to the channel, the first memory module including at least a first memory and a second memory, the first memory being a working memory and the second memory being a storage memory;

a second memory module connected to the channel, the second memory module including at least a third memory and a fourth memory, the third memory being a working memory and the fourth memory being a storage memory,

wherein the channel includes a first data line commonly connected to the first memory and the second memory, and

wherein the channel includes a second data line commonly connected to the third memory and the fourth memory.

2. The hybrid memory module structure of claim 1, wherein:

the first memory and third memory are the same type of memory; and

the second memory and fourth memory are the same type of memory.

3. The hybrid memory module structure of claim 2, wherein:

the first memory and third memory are volatile memories; and

the second memory and fourth memory are nonvolatile memories.

4. The hybrid memory module structure of claim 3, wherein:

the first memory and third memory are dynamic random access memories (DRAMs); and

the second memory and fourth memory are one of;

flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM).

5. The hybrid memory module structure of claim 1, wherein:

the first data line is not connected to the third or fourth memories, and

the second data line is not connected to the first or second memories.

6. The hybrid memory module structure of claim 5, wherein the first memory module further comprises a controller which allocates serial data received from a host through the first data line to the second memory and allocates non-serial data to the first memory.

7. The hybrid memory module structure of claim 1, wherein the first memory module further comprises a controller configured to classify data received from a host through the first data line and perform read and write operations on behalf of the first and second memories.

8. The hybrid memory module structure of claim 7, wherein the controller is configured to classify the data based on a marking of the data made by the host, or based on a transmission mode of the data.

9. The hybrid memory module structure of claim 1, wherein:

each memory of the first memory module includes one or more semiconductor chips; and

each memory of the second memory module includes one or more semiconductor chips.

10. The hybrid memory module structure of claim 9, wherein:

the first memory module is a dual inline memory module including at least four memories that include the first memory and second memory; and

the second memory module is a dual inline memory module including at least four memories that include the third memory and fourth memory.

11. The hybrid memory module structure of claim 1, wherein read and write operations of the first memory are faster than those of the second memory.

12. The hybrid memory module structure of claim 1, wherein the channel includes two slots, a first for connecting the first memory module, and a second for connecting the second memory module.

13. The hybrid memory module structure of claim 2, further comprising:

a first memory controller on the first hybrid memory module, the first memory controller configured to receive data from the first data line and to determine which of the first or second memories in which to store the received data; and

a second memory controller on the second hybrid memory module, the second memory controller configured to receive data from the second data line and to determine which of the third or fourth memories in which to store the received data.

14. A hybrid memory module structure comprising:

a channel for receiving data from and transmitting data to a device external to the hybrid memory module;

a first hybrid memory module connected to the channel, the first hybrid memory module including at least a first memory and a second memory, the first memory being a different type of memory from the second memory

a second hybrid memory module connected to the channel, the second memory module including at least a third memory and a fourth memory, the third memory being a different type of memory from the fourth memory;

a first memory controller on the first hybrid memory module, the first memory controller configured to receive data from the channel and to determine which of the first or second memories in which to store the received data; and

a second memory controller on the second hybrid memory module, the second memory controller configured to receive data from the channel and to determine which of the third or fourth memories in which to store the received data.

15. The hybrid memory module structure of claim 14, further comprising:

a first data line of the channel commonly connected to the first memory and the second memory through the first memory controller; and

a second data line of the channel commonly connected to the third memory and the fourth memory through the second memory controller.

16. An electronic device, comprising:

a first memory controller;

a first data line connected to the first memory controller and for communicating with an external host; and

a first hybrid memory module connected to the first memory controller, the first hybrid memory module including at least a first memory and a second memory, the first memory being a first type of memory and the second memory being a second type of memory,

wherein the first memory controller is configured to determine whether data received from the host is to be allocated to the first memory or the second memory.

17. The electronic device of claim 16, wherein the first type of memory is a working memory and the second type of memory is a storage memory.

18. The electronic device of claim 16, wherein the first memory controller is configured to classify the data based on a marking of the data made by the host, or based on a transmission mode of the data, in order to make the determination.

19. The electronic device of claim 16, further comprising:

a second memory controller;

a second data line connected to the second memory controller and for communicating with the external host; and

a second hybrid memory module connected to the second memory controller, the second hybrid memory module including at least a first memory and a second memory, the first memory of the second hybrid memory module being the first type of memory and the second memory of the second hybrid memory module being the second type of memory,

wherein the second memory controller is configured to determine whether data received from the host is to be allocated to the first memory of the second hybrid memory module or the second memory of the second hybrid memory module.

20. The electronic device of claim 19, wherein the first data line and the second data line are part of a single channel connected to the first hybrid memory module and the second hybrid memory module.