DATA WRITING METHOD, MEMOEY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

• US 20160110112A1
• Filed: 12/09/2014
• Published: 04/21/2016
• Est. Priority Date: 10/20/2014
• Status: Abandoned Application

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Yeh, Chih-Kang
• Application Number:
  US14/564,113
• Publication Number:
  US 20160110112A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A data writing method for a rewritable non-volatile memory module is provided. The method includes: if data belongs to a first pattern, using a first compression/decompression circuit to compress the data to generate compressed data and writing the compressed data into the rewritable non-volatile memory module; and if data belongs to a second pattern, using a second compression/decompression circuit to compress the data to generate another compressed data and writing the another compressed data into the rewritable non-volatile memory module, wherein the compression speed of the first compression/decompression circuit is higher than that of the second compression/decompression circuit, and the compression rate of the first compression/decompression circuit is lower than that of the second compression/decompression circuit.

Claims

1. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units, the data writing method comprising:

identifying whether data belongs to a first pattern or a second pattern;

if the data belongs to the first pattern, using a first compression/decompression circuit to compress the data to generate compressed data and writing the compressed data into the physical programming units; and

if the data belongs to the second pattern, using a second compression/decompression circuit to compress the data to generate another compressed data and writing the another compressed data into the physical programming units,

wherein a compression speed of the first compression/decompression circuit is higher than a compression speed of the second compression/decompression circuit, and a data compression rate of the first compression/decompression circuit is lower than a data compression rate of the second compression/decompression circuit.

2. The data writing method according to claim 1, wherein the step of identifying whether the data belongs to the first pattern or the second pattern comprises:

identifying first data instructed by a write command received from a host system as belonging to the first pattern; and

identifying second data read from the physical programming units as belonging to the second pattern.

3. The data writing method according to claim 2, wherein the step of using the first compression/decompression circuit to compress the data to generate the compressed data and writing the compressed data into the physical programming units comprises:

using the first compression/decompression circuit to compress the first data into first compressed data while transmitting the first data through a memory interface to the rewritable non-volatile memory module; and

writing the first compressed data into a first physical programming unit among the physical programming units.

4. The data writing method according to claim 3, further comprising:

performing a data merge operation to read one compressed data from a second physical programming unit among the physical programming units and using the first compression/decompression circuit to decompress the compressed data read from the second physical programming unit to obtain the second data,

wherein the step of using the second compression/decompression circuit to compress the data to generate the another compressed data and writing the another compressed data into the physical programming units comprises;

using the second compression/decompression circuit to compress the second data into second compressed data; and

writing the second compressed data into a third physical programming unit among the physical programming units.

5. The data writing method according to claim 3, further comprising:

performing a data merge operation to read the second data from a second physical programming unit among the physical programming units, wherein the second data is the data compressed by using the first compression/decompression circuit,

wherein the step of using the second compression/decompression circuit to compress the data to generate the another compressed data and writing the another compressed data into the physical programming units comprises;

using the second compression/decompression circuit to compress the second data into second compressed data; and

writing the second compressed data into a third physical programming unit among the physical programming units.

6. The data writing method according to claim 1, wherein the step of identifying whether the data belongs to the first pattern or the second pattern comprises:

determining whether each bit value of the data is the same;

if each bit value of the data is the same, identifying the data as belonging to the first pattern, wherein the step of using the first compression/decompression circuit to compress the data to generate the compressed data and writing the compressed data into the physical programming units is performed in a foreground execution mode; and

if each bit value of the data is not the same, identifying the data as belonging to the second pattern, wherein the step of using the second compression/decompression circuit to compress the data to generate the another compressed data and writing the another compressed data into the physical programming units is performed in a background execution mode.

7. A memory control circuit unit, configured to control a rewritable non-volatile memory, the memory control circuit unit comprising:

a host interface configured to be coupled to a host system;

a memory interface configured to be coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units;

a memory management circuit coupled to the host interface and the memory interface;

a first compression/decompression circuit coupled to the memory management circuit; and

a second compression/decompression circuit coupled to the memory management circuit, wherein the memory management circuit identifies whether data belongs to a first pattern or a second pattern,

if the data belongs to the first pattern, the first compression/decompression circuit compresses the data to generate compressed data, and the memory management circuit issues a command sequence to write the compressed data into the physical programming units, and

if the data belongs to the second pattern, the second compression/decompression circuit compresses the data to generate another compressed data, and the memory management circuit issues a command sequence to write the another compressed data into the physical programming units,

wherein a compression speed of the first compression/decompression circuit is higher than a compression speed of the second compression/decompression circuit, and a data compression rate of the first compression/decompression circuit is lower than a data compression rate of the second compression/decompression circuit.

8. The memory control circuit unit according to claim 7, wherein in the operation of identifying whether the data belongs to the first pattern or the second pattern, the memory management circuit identifies first data instructed by a write command received from a host system as belonging to the first pattern and identifies second data read from the physical programming units as belonging to the second pattern.

9. The memory control circuit unit according to claim 8, wherein in the operation of compressing the data to generate the compressed data and writing the compressed data into the physical programming units,

the first compression/decompression circuit compresses the first data into first compressed data while the memory management circuit transmits the first data through the memory interface to the rewritable non-volatile memory module,

wherein the first compressed data is written into a first physical programming unit among the physical programming units.

10. The memory control circuit unit according to claim 9, wherein the memory management circuit performs a data merge operation to read one compressed data from a second physical programming unit among the physical programming units, and the first compression/decompression circuit decompresses the compressed data read from the second physical programming unit to obtain the second data,

wherein in the operation of compressing the data to generate the another compressed data and writing the another compressed data into the physical programming units, the second compression/decompression circuit compresses the second data into second compressed data, and the memory management circuit writes the second compressed data into a third physical programming unit of the physical programming units.

11. The memory control circuit unit according to claim 9, wherein the memory management circuit performs a data merge operation to read the second data from the second physical programming unit among the physical programming units, wherein the second data is compressed by the first compression/decompression circuit,

wherein in the operation of compressing the data to generate the another compressed data and writing the another compressed data into the physical programming units, the second compression/decompression circuit compresses the second data into second compressed data, and the memory management circuit writes the second compressed data into a third physical programming unit among the physical programming units.

12. The memory control circuit unit according to claim 7, wherein in the operation of identifying whether the data belongs to the first pattern or the second pattern, the memory management circuit determines whether each bit value of the data is the same,

if each bit value of the data is the same, the memory management circuit identifies the data as belonging to the first pattern, wherein the operation of the first compression/decompression circuit compressing the data to generate the compressed data and the memory management circuit writing the compressed data into the physical programming units is performed in a foreground execution mode;

and

if each bit value of the data is not the same, the memory management circuit identifies the data as belonging to the second pattern, wherein the operation of the second compression/decompression circuit compressing the data to generate the another compressed data and the memory management circuit writing the another compressed data into the physical programming units is performed in a background execution mode.

13. A memory storage apparatus, comprising:

a connection interface unit configured to be coupled to a host system;

a rewritable non-volatile memory module having a plurality of physical erasing units, wherein each of the physical erasing units has a plurality of physical programming units; and

a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit identifies whether data belongs to a first pattern or a second pattern,

if the data belongs to the first pattern, the memory control circuit unit uses a first compression/decompression circuit to compress the data to generate compressed data and writes the compressed data into the physical programming units,

if the data belongs to the second pattern, the memory control circuit unit uses a second compression/decompression circuit to compress the data to generate compressed another compressed data and writes the another compressed data into the physical programming units,

wherein a compression speed of the first compression/decompression circuit is higher than a compression speed of the second compression/decompression circuit, and a data compression rate of the first compression/decompression circuit is lower than a data compression rate of the second compression/decompression circuit.

14. The memory storage apparatus according to claim 13, wherein in the operation of identifying whether the data belongs to the first pattern or the second pattern, the memory control circuit unit identifies first data instructed by a write command received from a host system as belonging to the first pattern and identifies second data read from the physical programming units as belonging to the second pattern.

15. The memory storage apparatus according to claim 14, wherein in the operation of using the first compression/decompression circuit to compress the data to generate the compressed data and writing the compressed data into the physical programming units,

the memory control circuit unit uses the first compression/decompression circuit to compress the first data into first compressed data while transmitting the first data through a memory interface to the rewritable non-volatile memory module,

wherein the first compressed data is written into a first physical programming unit among the physical programming units.

16. The memory storage apparatus according to claim 14, wherein the memory control circuit unit performs a data merge operation to read one compressed data from a second physical programming unit among the physical programming units and uses the first compression/decompression circuit to decompress decompresses the compressed data read from the second physical programming unit to obtain the second data,

wherein in the operation of using the second compression/decompression circuit to compress the data to generate the another compressed data and writing the another compressed data into the physical programming units, the memory control circuit unit uses the second compression/decompression circuit to compress the second data into second compressed data and writes the second compressed data into a third physical programming unit among the physical programming units.

17. The memory storage apparatus according to claim 14, wherein the memory control circuit unit performs a data merge operation to read the second data from the second physical programming unit among the physical programming units, wherein the second data is compressed by the first compression/decompression circuit,

wherein in the operation of using the second compression/decompression circuit to compress the data to generate the another compressed data and writing the another compressed data into the physical programming units, the memory control circuit unit uses the second compression/decompression circuit to compress the second data into second compressed data and writes the second compressed data into a third physical programming unit among the physical programming units.

18. The memory storage apparatus according to claim 13, wherein in the operation of identifying whether the data belongs to the first pattern or the second pattern, the memory control circuit unit determines whether each bit value of the data is the same,

if each bit value of the data is the same, the memory control circuit unit identifies the data as belonging to the first pattern, wherein the operation of compressing the data to generate the compressed data and writing the compressed data into the physical programming units is performed in a foreground execution mode;

and

if each bit value of the data is not the same, the memory control circuit unit identifies the data as belonging to the second pattern, wherein the operation of compressing the data to generate the another compressed data and writing the another compressed data into the physical programming units is performed in a background execution mode.